C1E enhanced halt state
C1E enhanced halt state — Introduced in the Pentium 4500J-series processors, the C1E halt state replaces the old C1 halt
state used on the Pentium 4 and most other x86 CPUs. The C1 halt state
is invoked when the operating system's idle process issues a HLT
command. (Windows does this constantly when not under a full load.)
Entering halt state, which is a lower-power state, will cut a CPU's
power consumption and heat production. Intel's new C1E halt state is
also invoked by the HLT command, but it turns down the entire CPU's
clock frequency (via multiplier control) and voltage in order to work
its mojo. This more robust halt state requires significantly less power
than the old C1 implementation.
C1E halt cranks the CPU bus
multiplier down to its lowest possible level on the 600-series
processors, which is 14X, so a P4 660 processor with the C1E halt state
active actually runs at 2.8GHz. I believe that C1E halt is also a
binary condition invoked by the HLT command; it's either on or it's off.
Extended HALT state is a low power state entered when the processor core has executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS. When the processor core executes the HALT instruction, the core is halted. The Extended HALT state is a lower power state than the HALT state or Stop Grant state.
Note: The Extended HALT (C1E) state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. The processor automatically transitions to a lower core frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus to core frequency ratio and then transition to the lower voltage (VID). While in the Extended HALT(C1E) state, the processor processes bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it first transitions the VID to the original value and then changes the bus to core frequency ratio back to the original value.
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