紧急求救呀 SUN V490 reboot -- -s 一直重启
V490 在reboot -- -S 之后就一直重启，OK模式下> boot disk1是可以启动的，下面是最大化自检的信息：求救呀，这个是怎么回事呀？
<*>
Hardware Power On
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 CMP1 CMP2 CMP3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done
Probing core system FRUs..
Probing Centerplane....part# 501-7224-01 serial# 011662
Safari min 100MHz, cumulative 100MHz;max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-05 serial# 116274
Probing System RSC.....part# 501-7314-01 serial# HG0ULJ
Probing PwrDistBoard...part# 375-3168-03 serial# O54274
Probing PowerSupply0...part# 300-1987-01 serial# P00810
Probing PowerSupply1...part# 300-1987-01 serial# P00470
Probing FCAL BPlane0...part# 501-5822-04 serial# 109754
Probing GPTwo Slot A...part# 501-6963-01 serial# 007455
CPU rated speed 1350MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...part# 501-6962-01 serial# 035584
CPU rated speed 1350MHz; ECache 8MB 3.3ns Done
Desired Safari Bus speed 150MHz, selecting 150MHz
Setting system bus speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 CMP1 CMP2 CMP3*
Configuring CPUs..........
..CMP0.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP0.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP1.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP1.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP3.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP3.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way Done
<*>
CPU Configuration Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online:CMP0 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP1 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP2 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online: *CMP3 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Executing POST w/%o0 = 0000.1000.0101.4043
0:0>
0:0>@(#)Sun Fire V480/V490 POST 4.22.34 2007/07/23 13:12
/export/delivery/delivery/4.22/4.22.34/post4.22.x/Camelot/cstone/integrated(root)
0:0>Copyright 2007 Sun Microsystems, Inc. All rights reserved
0:0>Jump from OBP->POST.
0:0>diag-switch? configuration variable set TRUE.
0:0>Keyswitch in DIAGNOSTIC POSITION.
0:0>Diag level set to MAX.
0:0>Verbosity level set to MAX.
0:0>MFG scrpt mode set NORM
0:0>I/O port set to serial TTYA.
0:0>
0:0>Start selftest...
0:0>Parking core 1
1:0>Parking core 1
2:0>Parking core 1
3:0>Parking core 1
0:0>CPUs present in system: 0:0 1:0 2:0 3:0
0:0>Test CPU(s).....
0:0>Init CPU
0:0> UltraSparc_IV Version 3.1
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>Probe Ecache
0:0> Size = 00000000.00800000...
0:0>Ecache Data Bitwalk
0:0>Ecache Address Bitwalk
0:0>Scrub and Setup Ecache
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
1:0>Init CPU
2:0>Init CPU
3:0>Init CPU
1:0> UltraSparc_IV Version 3.1
2:0> UltraSparc_IV Version 3.1
3:0> UltraSparc_IV Version 3.1
1:0>DMMU Registers Access
2:0>DMMU Registers Access
3:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
2:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
2:0>DMMU TLB TAGS Access
3:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
2:0>IMMU Registers Access
3:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
2:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
2:0>IMMU TLB TAGS Access
3:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0> Size = 00000000.00800000...
2:0>Probe Ecache
2:0> Size = 00000000.00800000...
3:0>Probe Ecache
3:0> Size = 00000000.00800000...
1:0>Ecache Data Bitwalk
2:0>Ecache Data Bitwalk
3:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
2:0>Ecache Address Bitwalk
3:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
2:0>Scrub and Setup Ecache
3:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
2:0>Setup and Enable DMMU
3:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
2:0>Setup DMMU Miss Handler
3:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
2:0>Test and Init Temp Mailbox
3:0>Test and Init Temp Mailbox
0:0>Init Scan/I2C.....
0:0>Initializing Scan Database
0:0>Mask DAR errors off
0:0>Init CDX DTL
0:0>Init DAR DTL
0:0>Enable Partial DAR error
0:0>Init DCS DTL
0:0>Init I2C
0:0>Unquiesce Safari
0:0>Margin all voltages to nominal
0:0>Scan ring integrity
0:0>Set Trip Temp CPU 0 to 110C
0:0>Set Trip Temp CPU 1 to 110C
0:0>Set Trip Temp CPU 2 to 110C
0:0>Set Trip Temp CPU 3 to 110C
0:0>TUES APR10 18:48:12 GMT 12
0:0>Safari quick check
0:0> to IO-bridge_0
0:0> to IO-bridge_1
0:0>Safari fullcheck
0:0> to IO-bridge_0
0:0> to IO-bridge_1
0:0>Disable CPU 0 error checking
0:0>Disable CPU 1 error checking
0:0>Disable CPU 2 error checking
0:0>Disable CPU 3 error checking
0:0>Basic Memory Test.....
0:0>Probe and Setup Memory
0:0>INFO: 1024MB Bank 0
0:0>INFO: 1024MB Bank 1
0:0>INFO: 1024MB Bank 2
0:0>INFO: 1024MB Bank 3
0:0>
0:0>Data Bitwalk on Master
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Address Bitwalk on Master
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 0: 00000000.00000000 to 00000000.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 1: 00000001.00000000 to 00000001.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 2: 00000002.00000000 to 00000002.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 3: 00000003.00000000 to 00000003.40000000.
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is426.
0:0>The Memory's Content Size value is b2dbc.
0:0>Success...Checksum on Memory Validated.
1:0>Safari quick check
1:0> to IO-bridge_0
1:0> to IO-bridge_1
1:0>Safari fullcheck
1:0> to IO-bridge_0
1:0> to IO-bridge_1
2:0>Safari quick check
2:0> to IO-bridge_0
2:0> to IO-bridge_1
2:0>Safari fullcheck
2:0> to IO-bridge_0
2:0> to IO-bridge_1
3:0>Safari quick check
3:0> to IO-bridge_0
3:0> to IO-bridge_1
3:0>Safari fullcheck
3:0> to IO-bridge_0
3:0> to IO-bridge_1
1:0>Probe and Setup Memory
2:0>Probe and Setup Memory
3:0>Probe and Setup Memory
1:0>INFO: 1024MB Bank 0
1:0>INFO: 1024MB Bank 1
1:0>INFO: 1024MB Bank 2
1:0>INFO: 1024MB Bank 3
1:0>
2:0>INFO: 1024MB Bank 0
2:0>INFO: 1024MB Bank 1
2:0>INFO: 1024MB Bank 2
2:0>INFO: 1024MB Bank 3
2:0>
3:0>INFO: 1024MB Bank 0
3:0>INFO: 1024MB Bank 1
3:0>INFO: 1024MB Bank 2
3:0>INFO: 1024MB Bank 3
3:0>
1:0>Set Mailbox
2:0>Set Mailbox
3:0>Set Mailbox
0:0>Data Bitwalk on Slave 1
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Data Bitwalk on Slave 2
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Data Bitwalk on Slave 3
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Address Bitwalk on Slave 1
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 0: 00000010.00000000 to 00000010.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 1: 00000011.00000000 to 00000011.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 2: 00000012.00000000 to 00000012.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 3: 00000013.00000000 to 00000013.40000000.
0:0>Address Bitwalk on Slave 2
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 0: 00000020.00000000 to 00000020.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 1: 00000021.00000000 to 00000021.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 2: 00000022.00000000 to 00000022.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 3: 00000023.00000000 to 00000023.40000000.
0:0>Address Bitwalk on Slave 3
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 0: 00000030.00000000 to 00000030.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 1: 00000031.00000000 to 00000031.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 2: 00000032.00000000 to 00000032.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 3: 00000033.00000000 to 00000033.40000000.
1:0>Setup Final DMMU Entries
2:0>Setup Final DMMU Entries
3:0>Setup Final DMMU Entries
1:0>Map Slave POST to master memory
2:0>Map Slave POST to master memory
3:0>Map Slave POST to master memory
1:0>8k DMMU TLB 0 Data
2:0>8k DMMU TLB 0 Data
3:0>8k DMMU TLB 0 Data
0:0>Full CPU Test.....
0:0>8k DMMU TLB 0 Data
1:0>8k DMMU TLB 1 Data
2:0>8k DMMU TLB 1 Data
3:0>8k DMMU TLB 1 Data
0:0>8k DMMU TLB 1 Data
1:0>8k DMMU TLB 0 Tags
2:0>8k DMMU TLB 0 Tags
3:0>8k DMMU TLB 0 Tags
0:0>8k DMMU TLB 0 Tags
1:0>8k DMMU TLB 1 Tags
2:0>8k DMMU TLB 1 Tags
3:0>8k DMMU TLB 1 Tags
0:0>8k DMMU TLB 1 Tags
1:0>8k IMMU TLB Data
2:0>8k IMMU TLB Data
3:0>8k IMMU TLB Data
0:0>8k IMMU TLB Data
1:0>8k IMMU TLB Tags
2:0>8k IMMU TLB Tags
3:0>8k IMMU TLB Tags
0:0>8k IMMU TLB Tags
1:0>Instruction Cache Tag RAM
2:0>Instruction Cache Tag RAM
3:0>Instruction Cache Tag RAM
0:0>Instruction Cache Tag RAM
1:0>Instruction Cache RAM
2:0>Instruction Cache RAM
3:0>Instruction Cache RAM
0:0>Instruction Cache RAM
1:0>I-Cache Valid/Predict TAGS Test
2:0>I-Cache Valid/Predict TAGS Test
3:0>I-Cache Valid/Predict TAGS Test
0:0>I-Cache Valid/Predict TAGS Test
1:0>I-Cache Branch Predict Array Test
2:0>I-Cache Branch Predict Array Test
3:0>I-Cache Branch Predict Array Test
0:0>I-Cache Branch Predict Array Test
1:0>Instruction Cache Snoop Tag Field
2:0>Instruction Cache Snoop Tag Field
3:0>Instruction Cache Snoop Tag Field
0:0>Instruction Cache Snoop Tag Field
1:0>Flush D/W caches
2:0>Flush D/W caches
3:0>Flush D/W caches
0:0>Flush D/W caches
1:0>Data Cache RAM
2:0>Data Cache RAM
3:0>Data Cache RAM
1:0>Data Cache Tags
2:0>Data Cache Tags
0:0>Data Cache RAM
3:0>Data Cache Tags
1:0>Data Micro Tags
2:0>Data Micro Tags
0:0>Data Cache Tags
3:0>Data Micro Tags
1:0>D-Cache SnoopTags Test
2:0>D-Cache SnoopTags Test
0:0>Data Micro Tags
3:0>D-Cache SnoopTags Test
0:0>D-Cache SnoopTags Test
1:0>WCache RAM
2:0>WCache RAM
3:0>WCache RAM
1:0>WCache Tags
2:0>WCache Tags
0:0>WCache RAM
3:0>WCache Tags
1:0>W-Cache Valid bit Test
2:0>W-Cache Valid bit Test
0:0>WCache Tags
3:0>W-Cache Valid bit Test
1:0>W-Cache Bank valid bit Test
2:0>W-Cache Bank valid bit Test
0:0>W-Cache Valid bit Test
3:0>W-Cache Bank valid bit Test
1:0>W-Cache SnoopTAGS Test
2:0>W-Cache SnoopTAGS Test
0:0>W-Cache Bank valid bit Test
3:0>W-Cache SnoopTAGS Test
0:0>W-Cache SnoopTAGS Test
1:0>Prefetch Cache RAM
2:0>Prefetch Cache RAM
3:0>Prefetch Cache RAM
1:0>Prefetch Cache Tags
2:0>Prefetch Cache Tags
0:0>Prefetch Cache RAM
3:0>Prefetch Cache Tags
1:0>P-Cache SnoopTags Test
2:0>P-Cache SnoopTags Test
0:0>Prefetch Cache Tags
3:0>P-Cache SnoopTags Test
1:0>P-Cache Status Data Test
2:0>P-Cache Status Data Test
0:0>P-Cache SnoopTags Test
3:0>P-Cache Status Data Test
1:0>Branch Prediction Initialization
2:0>Branch Prediction Initialization
0:0>P-Cache Status Data Test
3:0>Branch Prediction Initialization
0:0>Branch Prediction Initialization
1:0>Scrub Memory
2:0>Scrub Memory
3:0>Scrub Memory
0:0>Memory Block.....
0:0>Scrub Memory
1:0>Print Mem Config
1:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1:0>Memory in non-interleave config:
1:0> Bank 0 1024MB : 00000010.00000000 -> 00000010.40000000.
1:0> Bank 1 1024MB : 00000011.00000000 -> 00000011.40000000.
1:0> Bank 2 1024MB : 00000012.00000000 -> 00000012.40000000.
1:0> Bank 3 1024MB : 00000013.00000000 -> 00000013.40000000.
2:0>Print Mem Config
2:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:0>Memory in non-interleave config:
2:0> Bank 0 1024MB : 00000020.00000000 -> 00000020.40000000.
2:0> Bank 1 1024MB : 00000021.00000000 -> 00000021.40000000.
2:0> Bank 2 1024MB : 00000022.00000000 -> 00000022.40000000.
2:0> Bank 3 1024MB : 00000023.00000000 -> 00000023.40000000.
3:0>Print Mem Config
3:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3:0>Memory in non-interleave config:
3:0> Bank 0 1024MB : 00000030.00000000 -> 00000030.40000000.
3:0> Bank 1 1024MB : 00000031.00000000 -> 00000031.40000000.
3:0> Bank 2 1024MB : 00000032.00000000 -> 00000032.40000000.
3:0> Bank 3 1024MB : 00000033.00000000 -> 00000033.40000000.
0:0>Print Mem Config
0:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:0>Memory in non-interleave config:
0:0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.
0:0> Bank 1 1024MB : 00000001.00000000 -> 00000001.40000000.
0:0> Bank 2 1024MB : 00000002.00000000 -> 00000002.40000000.
0:0> Bank 3 1024MB : 00000003.00000000 -> 00000003.40000000.
1:0>Quick Block Mem Test
2:0>Quick Block Mem Test
1:0>Quick Test 16777216 bytes at 00000010.00000000
2:0>Quick Test 16777216 bytes at 00000020.00000000
3:0>Quick Block Mem Test
0:0>Quick Block Mem Test
3:0>Quick Test 16777216 bytes at 00000030.00000000
0:0>Quick Test 16777216 bytes at 00000000.00600000
0:0>40% Done...
1:0>Flush Caches
2:0>Flush Caches
3:0>Flush Caches
0:0>Flush Caches
1:0>Get code in ecache.
2:0>Get code in ecache.
3:0>Get code in ecache.
0:0>Get code in ecache.
0:0>IO-Bridge Tests.....
0:0>IO-Bridge unit 0 init test
0:0>IO-Bridge unit 1 init test
1:0>Enabling core 1
2:0>Enabling core 1
3:0>Enabling core 1
0:0>Enabling core 1
0:1>Init CPU
1:1>Init CPU
0:1> UltraSparc_IV Version 3.1
1:1> UltraSparc_IV Version 3.1
2:1>Init CPU
3:1>Init CPU
2:1> UltraSparc_IV Version 3.1
3:1> UltraSparc_IV Version 3.1
0:1>DMMU Registers Access
1:1>DMMU Registers Access
2:1>DMMU Registers Access
3:1>DMMU Registers Access
0:1>DMMU TLB DATA RAM Access
1:1>DMMU TLB DATA RAM Access
2:1>DMMU TLB DATA RAM Access
3:1>DMMU TLB DATA RAM Access
0:1>DMMU TLB TAGS Access
1:1>DMMU TLB TAGS Access
2:1>DMMU TLB TAGS Access
3:1>DMMU TLB TAGS Access
0:1>IMMU Registers Access
1:1>IMMU Registers Access
2:1>IMMU Registers Access
3:1>IMMU Registers Access
0:1>IMMU TLB DATA RAM Access
1:1>IMMU TLB DATA RAM Access
2:1>IMMU TLB DATA RAM Access
3:1>IMMU TLB DATA RAM Access
0:1>IMMU TLB TAGS Access
1:1>IMMU TLB TAGS Access
2:1>IMMU TLB TAGS Access
3:1>IMMU TLB TAGS Access
0:1>Probe Ecache
0:1> Size = 00000000.00800000...
1:1>Probe Ecache
1:1> Size = 00000000.00800000...
2:1>Probe Ecache
2:1> Size = 00000000.00800000...
3:1>Probe Ecache
3:1> Size = 00000000.00800000...
0:1>Ecache Data Bitwalk
1:1>Ecache Data Bitwalk
2:1>Ecache Data Bitwalk
3:1>Ecache Data Bitwalk
0:1>Ecache Address Bitwalk
1:1>Ecache Address Bitwalk
2:1>Ecache Address Bitwalk
3:1>Ecache Address Bitwalk
0:1>Scrub and Setup Ecache
1:1>Scrub and Setup Ecache
2:1>Scrub and Setup Ecache
3:1>Scrub and Setup Ecache
0:1>Setup and Enable DMMU
1:1>Setup and Enable DMMU
2:1>Setup and Enable DMMU
3:1>Setup and Enable DMMU
0:1>Setup DMMU Miss Handler
1:1>Setup DMMU Miss Handler
2:1>Setup DMMU Miss Handler
3:1>Setup DMMU Miss Handler
0:1>Test and Init Temp Mailbox
1:1>Test and Init Temp Mailbox
2:1>Test and Init Temp Mailbox
3:1>Test and Init Temp Mailbox
0:1>Set Mailbox
1:1>Set Mailbox
2:1>Set Mailbox
3:1>Set Mailbox
0:1>Setup Final DMMU Entries
1:1>Setup Final DMMU Entries
2:1>Setup Final DMMU Entries
3:1>Setup Final DMMU Entries
0:1>Map Slave POST to master memory
1:1>Map Slave POST to master memory
2:1>Map Slave POST to master memory
3:1>Map Slave POST to master memory
0:1>8k DMMU TLB 0 Data
1:1>8k DMMU TLB 0 Data
2:1>8k DMMU TLB 0 Data
3:1>8k DMMU TLB 0 Data
0:1>8k DMMU TLB 1 Data
1:1>8k DMMU TLB 1 Data
2:1>8k DMMU TLB 1 Data
3:1>8k DMMU TLB 1 Data
0:1>8k DMMU TLB 0 Tags
1:1>8k DMMU TLB 0 Tags
2:1>8k DMMU TLB 0 Tags
3:1>8k DMMU TLB 0 Tags
0:1>8k DMMU TLB 1 Tags
1:1>8k DMMU TLB 1 Tags
2:1>8k DMMU TLB 1 Tags
3:1>8k DMMU TLB 1 Tags
0:1>8k IMMU TLB Data
1:1>8k IMMU TLB Data
2:1>8k IMMU TLB Data
3:1>8k IMMU TLB Data
0:1>8k IMMU TLB Tags
1:1>8k IMMU TLB Tags
2:1>8k IMMU TLB Tags
3:1>8k IMMU TLB Tags
0:1>Instruction Cache Tag RAM
1:1>Instruction Cache Tag RAM
2:1>Instruction Cache Tag RAM
3:1>Instruction Cache Tag RAM
0:1>Instruction Cache RAM
1:1>Instruction Cache RAM
2:1>Instruction Cache RAM
3:1>Instruction Cache RAM
0:1>I-Cache Valid/Predict TAGS Test
1:1>I-Cache Valid/Predict TAGS Test
2:1>I-Cache Valid/Predict TAGS Test
3:1>I-Cache Valid/Predict TAGS Test
0:1>I-Cache Branch Predict Array Test
1:1>I-Cache Branch Predict Array Test
2:1>I-Cache Branch Predict Array Test
3:1>I-Cache Branch Predict Array Test
0:1>Instruction Cache Snoop Tag Field
1:1>Instruction Cache Snoop Tag Field
2:1>Instruction Cache Snoop Tag Field
3:1>Instruction Cache Snoop Tag Field
0:1>Flush D/W caches
1:1>Flush D/W caches
2:1>Flush D/W caches
3:1>Flush D/W caches
0:1>Data Cache RAM
1:1>Data Cache RAM
2:1>Data Cache RAM
3:1>Data Cache RAM
0:1>Data Cache Tags
1:1>Data Cache Tags
2:1>Data Cache Tags
3:1>Data Cache Tags
0:1>Data Micro Tags
1:1>Data Micro Tags
2:1>Data Micro Tags
3:1>Data Micro Tags
0:1>D-Cache SnoopTags Test
1:1>D-Cache SnoopTags Test
2:1>D-Cache SnoopTags Test
3:1>D-Cache SnoopTags Test
0:1>WCache RAM
1:1>WCache RAM
2:1>WCache RAM
3:1>WCache RAM
0:1>WCache Tags
1:1>WCache Tags
2:1>WCache Tags
3:1>WCache Tags
0:1>W-Cache Valid bit Test
1:1>W-Cache Valid bit Test
2:1>W-Cache Valid bit Test
3:1>W-Cache Valid bit Test
0:1>W-Cache Bank valid bit Test
1:1>W-Cache Bank valid bit Test
2:1>W-Cache Bank valid bit Test
3:1>W-Cache Bank valid bit Test
0:1>W-Cache SnoopTAGS Test
1:1>W-Cache SnoopTAGS Test
2:1>W-Cache SnoopTAGS Test
3:1>W-Cache SnoopTAGS Test
0:1>Prefetch Cache RAM
1:1>Prefetch Cache RAM
2:1>Prefetch Cache RAM
3:1>Prefetch Cache RAM
0:1>Prefetch Cache Tags
1:1>Prefetch Cache Tags
2:1>Prefetch Cache Tags
3:1>Prefetch Cache Tags
0:1>P-Cache SnoopTags Test
1:1>P-Cache SnoopTags Test
2:1>P-Cache SnoopTags Test
3:1>P-Cache SnoopTags Test
0:1>P-Cache Status Data Test
1:1>P-Cache Status Data Test
2:1>P-Cache Status Data Test
3:1>P-Cache Status Data Test
0:1>Branch Prediction Initialization
1:1>Branch Prediction Initialization
2:1>Branch Prediction Initialization
3:1>Branch Prediction Initialization
0:1>Print Mem Config
0:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1:1>Print Mem Config
1:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:1>Print Mem Config
2:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3:1>Print Mem Config
3:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:1>Flush Caches
1:1>Flush Caches
2:1>Flush Caches
3:1>Flush Caches
0:1>Get code in ecache.
1:1>Get code in ecache.
2:1>Get code in ecache.
3:1>Get code in ecache.
0:1>FPU Registers and Data Path
1:1>FPU Registers and Data Path
2:1>FPU Registers and Data Path
3:1>FPU Registers and Data Path
0:1>FPU Move Registers
1:1>FPU Move Registers
2:1>FPU Move Registers
3:1>FPU Move Registers
0:1>FSR Read/Write
1:1>FSR Read/Write
2:1>FSR Read/Write
3:1>FSR Read/Write
0:1>FPU Branch Instructions
1:1>FPU Branch Instructions
2:1>FPU Branch Instructions
3:1>FPU Branch Instructions
0:1>FPU Functional Test
1:1>FPU Functional Test
2:1>FPU Functional Test
3:1>FPU Functional Test
0:1>FPU BLOCK REG TEST
1:1>FPU BLOCK REG TEST
2:1>FPU BLOCK REG TEST
3:1>FPU BLOCK REG TEST
0:0>IO-Bridge unit 0 reg test
0:0>IO-Bridge unit 0 mem test
0:0>IO-Bridge unit 0 PCI DMA A test
0:0>IO-Bridge unit 0 PCI DMA B test
0:0>IO-Bridge unit 0 PCI mergtest
0:0>IO-Bridge unit 0 PCI iommu test
0:0>IO-Bridge unit 0 PCI stc test
0:0>IO-Bridge unit 0 interrupt test
0:0>IO-Bridge unit 1 reg test
0:0>IO-Bridge unit 1 mem test
0:0>IO-Bridge unit 1 PCI DMA C test
0:0>IO-Bridge unit 1 PCI DMA D test
0:0>IO-Bridge unit 1 PCI mergtest
0:0>IO-Bridge unit 1 PCI iommu test
0:0>IO-Bridge unit 1 PCI stc test
0:0>IO-Bridge unit 1 interrupt test
1:0>IO-Bridge unit 0 init test
1:0>IO-Bridge unit 0 reg test
1:0>IO-Bridge unit 0 mem test
1:0>IO-Bridge unit 0 PCI DMA test
1:0>IO-Bridge unit 0 PCI mergtest
1:0>IO-Bridge unit 0 PCI iommu test
1:0>IO-Bridge unit 0 PCI stc test
1:0>IO-Bridge unit 0 interrupt test
1:0>IO-Bridge unit 1 init test
1:0>IO-Bridge unit 1 reg test
1:0>IO-Bridge unit 1 mem test
1:0>IO-Bridge unit 1 PCI DMA test
1:0>IO-Bridge unit 1 PCI mergtest
1:0>IO-Bridge unit 1 PCI iommu test
1:0>IO-Bridge unit 1 PCI stc test
1:0>IO-Bridge unit 1 interrupt test
2:0>IO-Bridge unit 0 init test
2:0>IO-Bridge unit 0 reg test
2:0>IO-Bridge unit 0 mem test
2:0>IO-Bridge unit 0 PCI DMA test
2:0>IO-Bridge unit 0 PCI mergtest
2:0>IO-Bridge unit 0 PCI iommu test
2:0>IO-Bridge unit 0 PCI stc test
2:0>IO-Bridge unit 0 interrupt test
2:0>IO-Bridge unit 1 init test
2:0>IO-Bridge unit 1 reg test
2:0>IO-Bridge unit 1 mem test
2:0>IO-Bridge unit 1 PCI DMA test
2:0>IO-Bridge unit 1 PCI mergtest
2:0>IO-Bridge unit 1 PCI iommu test
2:0>IO-Bridge unit 1 PCI stc test
2:0>IO-Bridge unit 1 interrupt test
3:0>IO-Bridge unit 0 init test
3:0>IO-Bridge unit 0 reg test
3:0>IO-Bridge unit 0 mem test
3:0>IO-Bridge unit 0 PCI DMA test
3:0>IO-Bridge unit 0 PCI mergtest
3:0>IO-Bridge unit 0 PCI iommu test
3:0>IO-Bridge unit 0 PCI stc test
3:0>IO-Bridge unit 0 interrupt test
3:0>IO-Bridge unit 1 init test
3:0>IO-Bridge unit 1 reg test
3:0>IO-Bridge unit 1 mem test
3:0>IO-Bridge unit 1 PCI DMA test
3:0>IO-Bridge unit 1 PCI mergtest
3:0>IO-Bridge unit 1 PCI iommu test
3:0>IO-Bridge unit 1 PCI stc test
3:0>IO-Bridge unit 1 interrupt test
1:0>FPU Registers and Data Path
2:0>FPU Registers and Data Path
3:0>FPU Registers and Data Path
0:1>FPU Registers and Data Path
1:1>FPU Registers and Data Path
2:1>FPU Registers and Data Path
3:1>FPU Registers and Data Path
0:0>FPU Registers and Data Path
1:0>FPU Move Registers
2:0>FPU Move Registers
3:0>FPU Move Registers
0:1>FPU Move Registers
1:1>FPU Move Registers
2:1>FPU Move Registers
3:1>FPU Move Registers
0:0>FPU Move Registers
1:0>FSR Read/Write
2:0>FSR Read/Write
3:0>FSR Read/Write
0:1>FSR Read/Write
1:1>FSR Read/Write
2:1>FSR Read/Write
3:1>FSR Read/Write
0:0>FSR Read/Write
1:0>FPU Branch Instructions
2:0>FPU Branch Instructions
3:0>FPU Branch Instructions
0:1>FPU Branch Instructions
1:1>FPU Branch Instructions
2:1>FPU Branch Instructions
3:1>FPU Branch Instructions
0:0>FPU Branch Instructions
1:0>FPU Functional Test
2:0>FPU Functional Test
3:0>FPU Functional Test
0:1>FPU Functional Test
1:1>FPU Functional Test
2:1>FPU Functional Test
3:1>FPU Functional Test
0:0>FPU Functional Test
1:0>FPU BLOCK REG TEST
2:0>FPU BLOCK REG TEST
3:0>FPU BLOCK REG TEST
0:1>FPU BLOCK REG TEST
1:1>FPU BLOCK REG TEST
2:1>FPU BLOCK REG TEST
3:1>FPU BLOCK REG TEST
0:0>FPU BLOCK REG TEST
1:0>Calculating memory test time
2:0>Calculating memory test time
3:0>Calculating memory test time
0:1>Calculating memory test time
1:1>Calculating memory test time
1:0>
1:0>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
2:0>
2:0>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
3:0>
3:0>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
0:1>
0:1>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
1:1>
1:1>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
2:1>Calculating memory test time
3:1>Calculating memory test time
0:0>Full Memory Test.....
1:0>
1:0>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
2:0>
2:0>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
3:0>
3:0>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
0:1>
0:1>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
1:1>
1:1>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
2:1>
2:1>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
3:1>
3:1>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
0:0>Calculating memory test time
2:1>
2:1>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
3:1>
3:1>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
0:0>
0:0>INFO: The expected TIMEOUT for the block memory tests can exceed 4 minutes.
1:0>Block Memory
2:0>Block Memory
3:0>Block Memory
0:0>
0:0>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 224 minutes.
1:0>Test 1073741824 bytes on bank 0....
2:0>Test 1073741824 bytes on bank 0....
3:0>Test 1073741824 bytes on bank 0....
1:0>0% Done...
0:0>Block Memory
0:0>Test 1067450368 bytes on bank 0....
0:0>0% Done...
0:0>2% Done...
0:0>3% Done...
0:0>4% Done...
0:0>6% Done...
0:0>7% Done...
0:0>9% Done...
0:0>10% Done...
0:0>11% Done...
0:0>13% Done...
0:0>14% Done...
0:0>16% Done...
0:0>17% Done...
0:0>18% Done...
0:0>20% Done...
0:0>21% Done...
0:0>22% Done...
0:0>24% Done...
0:0>25% Done...
0:0>27% Done...
0:0>28% Done...
0:0>29% Done...
0:0>31% Done...
0:0>32% Done...
0:0>34% Done...
0:0>35% Done...
0:0>36% Done...
0:0>38% Done...
0:0>39% Done...
0:0>41% Done...
0:0>42% Done...
0:0>43% Done...
0:0>45% Done...
0:0>46% Done...
0:0>48% Done...
0:0>49% Done...
0:0>50% Done...
0:0>52% Done...
0:0>53% Done...
0:0>55% Done...
0:0>56% Done...
0:0>57% Done...
0:0>59% Done...
0:0>60% Done...
0:0>62% Done...
0:0>63% Done...
0:0>64% Done...
0:0>66% Done...
0:0>67% Done...
0:0>69% Done...
0:0>70% Done...
0:0>71% Done...
0:0>73% Done...
0:0>74% Done...
0:0>76% Done...
0:0>77% Done...
0:0>78% Done...
0:0>80% Done...
0:0>81% Done...
0:0>83% Done...
0:0>84% Done...
0:0>85% Done...
0:0>87% Done...
0:0>88% Done...
0:0>90% Done...
0:0>91% Done...
2:0>Test 1073741824 bytes on bank 1....
3:0>Test 1073741824 bytes on bank 1....
1:0>Test 1073741824 bytes on bank 1....
0:0>92% Done...
0:0>94% Done...
0:0>95% Done...
0:0>97% Done...
0:0>98% Done...
0:0>99% Done...
0:0>Test 1073741824 bytes on bank 1....
0:0>0% Done...
0:0>2% Done...
0:0>3% Done...
0:0>4% Done...
0:0>6% Done...
0:0>7% Done...
0:0>9% Done...
0:0>10% Done...
0:0>11% Done...
0:0>13% Done...
0:0>14% Done...
0:0>15% Done...
0:0>17% Done...
0:0>18% Done...
0:0>20% Done...
0:0>21% Done...
0:0>22% Done...
0:0>24% Done...
0:0>25% Done...
0:0>27% Done...
0:0>28% Done...
0:0>29% Done...
0:0>31% Done...
0:0>32% Done...
0:0>34% Done...
0:0>35% Done...
0:0>36% Done...
0:0>38% Done...
0:0>39% Done...
0:0>40% Done...
0:0>42% Done...
0:0>43% Done...
0:0>45% Done...
0:0>46% Done...
0:0>47% Done...
0:0>49% Done...
0:0>50% Done...
0:0>52% Done...
0:0>53% Done...
0:0>54% Done...
0:0>56% Done...
0:0>57% Done...
0:0>59% Done...
0:0>60% Done...
0:0>61% Done...
0:0>63% Done...
0:0>64% Done...
0:0>65% Done...
0:0>67% Done...
0:0>68% Done...
0:0>70% Done...
0:0>71% Done...
0:0>72% Done...
0:0>74% Done...
0:0>75% Done...
0:0>77% Done...
0:0>78% Done...
0:0>79% Done...
0:0>81% Done...
0:0>82% Done...
2:0>Test 1073741824 bytes on bank 2....
3:0>Test 1073741824 bytes on bank 2....
1:0>Test 1073741824 bytes on bank 2....
0:0>84% Done...
0:0>85% Done...
0:0>86% Done...
0:0>88% Done...
0:0>89% Done...
0:0>90% Done...
0:0>92% Done...
0:0>93% Done...
0:0>95% Done...
0:0>96% Done...
0:0>97% Done...
0:0>99% Done...
0:0>Test 1073741824 bytes on bank 2....
0:0>0% Done...
0:0>2% Done...
0:0>3% Done...
0:0>4% Done...
0:0>6% Done...
0:0>7% Done...
0:0>9% Done...
0:0>10% Done...
0:0>11% Done...
0:0>13% Done...
0:0>14% Done...
0:0>15% Done...
0:0>17% Done...
0:0>18% Done...
0:0>20% Done...
0:0>21% Done...
0:0>22% Done...
0:0>24% Done...
0:0>25% Done...
0:0>27% Done...
0:0>28% Done...
0:0>29% Done...
0:0>31% Done...
0:0>32% Done...
0:0>34% Done...
0:0>35% Done...
0:0>36% Done...
0:0>38% Done...
0:0>39% Done...
0:0>40% Done...
0:0>42% Done...
0:0>43% Done...
0:0>45% Done...
0:0>46% Done...
0:0>47% Done...
0:0>49% Done...
0:0>50% Done...
0:0>52% Done...
0:0>53% Done...
0:0>54% Done...
0:0>56% Done...
0:0>57% Done...
0:0>59% Done...
0:0>60% Done...
0:0>61% Done...
0:0>63% Done...
0:0>64% Done...
0:0>65% Done...
0:0>67% Done...
0:0>68% Done...
0:0>70% Done...
0:0>71% Done...
0:0>72% Done...
0:0>74% Done...
0:0>75% Done...
2:0>Test 1073741824 bytes on bank 3....
3:0>Test 1073741824 bytes on bank 3....
1:0>Test 1073741824 bytes on bank 3....
0:0>77% Done...
0:0>78% Done...
0:0>79% Done...
0:0>81% Done...
0:0>82% Done...
0:0>84% Done...
0:0>85% Done...
0:0>86% Done...
0:0>88% Done...
0:0>89% Done...
0:0>90% Done...
0:0>92% Done...
0:0>93% Done...
0:0>95% Done...
0:0>96% Done...
0:0>97% Done...
0:0>99% Done...
0:0>Test 1073741824 bytes on bank 3....
0:0>0% Done...
0:0>2% Done...
0:0>3% Done...
0:0>4% Done...
0:0>6% Done...
0:0>7% Done...
0:0>9% Done...
0:0>10% Done...
0:0>11% Done...
0:0>13% Done...
0:0>14% Done...
0:0>15% Done...
0:0>17% Done...
0:0>18% Done...
0:0>20% Done...
0:0>21% Done...
0:0>22% Done...
0:0>24% Done...
0:0>25% Done...
0:0>27% Done...
0:0>28% Done...
0:0>29% Done...
0:0>31% Done...
0:0>32% Done...
0:0>34% Done...
0:0>35% Done...
0:0>36% Done...
0:0>38% Done...
0:0>39% Done...
0:0>40% Done...
0:0>42% Done...
0:0>43% Done...
0:0>45% Done...
0:0>46% Done...
0:0>47% Done...
0:0>49% Done...
0:0>50% Done...
0:0>52% Done...
0:0>53% Done...
0:0>54% Done...
0:0>56% Done...
0:0>57% Done...
0:0>59% Done...
0:0>60% Done...
0:0>61% Done...
0:0>63% Done...
0:0>64% Done...
0:0>65% Done...
0:0>67% Done...
0:0>68% Done...
0:0>70% Done...
0:0>71% Done...
0:0>72% Done...
0:0>74% Done...
0:0>75% Done...
0:0>77% Done...
0:0>78% Done...
0:0>79% Done...
0:0>81% Done...
0:0>82% Done...
0:0>84% Done...
0:0>85% Done...
0:0>86% Done...
0:0>88% Done...
0:0>89% Done...
0:0>90% Done...
0:0>92% Done...
0:0>93% Done...
0:0>95% Done...
0:0>96% Done...
0:0>97% Done...
0:0>99% Done...
0:0>
0:0>Motherboard/Centerplane Board Part Number:
0:0> 5017224-01-50
0:0>IO/Riser Board Part Number:
0:0> 5015820-05-50
0:0>CPUA Board Part Number:
0:0> 5016963-01-50
0:0>CPUB Board Part Number:
0:0> 5016962-01-54
0:0>Enable Errors.....
0:0>Turn IO-Bridge 0 errors on
0:0>Turn IO-Bridge 1 errors on
0:0>Turn CPU 0 errors on
0:0>Turn CPU 1 errors on
0:0>Turn CPU 2 errors on
0:0>Turn CPU 3 errors on
0:0>Turn Module A DCDS errors on
0:0>Turn Module B DCDS errors on
0:0>Turn DCS errors on
0:0>Turn DAR errors on
0:0>Turn error traps on
0:0>INFO:
0:0> POST Passed all devices.
0:0>POST: Return to OBP.
CPU0: System POST Completed
Pass/Fail Status= 0000.0000.0000.0000
ESB Overall Status= ffff.ffff.ffff.ffff
<*>
POST Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 CMP1 CMP2 CMP3*
Configuring CPUs..........
..CMP0.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP0.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP1.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP1.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP3.0 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way
..CMP3.1 Speed 1350MHz Ecache8MB 3.3ns mode=5-5-5(2) 2-way Done
<*>
CPU Configuration Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online:CMP0 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP1 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP2 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online: *CMP3 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Enabling system bus....... CMP0 CMP1 CMP2 CMP3 Done
Probing Memory............
Probing CMP0 memory configuration
NGDIMM#0 part# 501-7385-01 serial# A235F6,256MB + 256MB,SC#0
NGDIMM#1 part# 501-7385-01 serial# A1D636,256MB + 256MB,SC#0
NGDIMM#2 part# 501-7385-01 serial# A1DBC9,256MB + 256MB,SC#0
NGDIMM#3 part# 501-7385-01 serial# A1D6C8,256MB + 256MB,SC#0
NGDIMM#4 part# 501-7385-01 serial# A235F7,256MB + 256MB,SC#0
NGDIMM#5 part# 501-7385-01 serial# A235F8,256MB + 256MB,SC#0
NGDIMM#6 part# 501-7385-01 serial# A2022E,256MB + 256MB,SC#0
NGDIMM#7 part# 501-7385-01 serial# A235EB,256MB + 256MB,SC#0
Probing CMP1 memory configuration
NGDIMM#0 part# 501-5030-03 serial# L11GTA,256MB + 256MB,SC#0
NGDIMM#1 part# 501-5030-03 serial# L26ZJK,256MB + 256MB,SC#0
NGDIMM#2 part# 501-5030-03 serial# L26ZKC,256MB + 256MB,SC#0
NGDIMM#3 part# 501-5030-03 serial# L26ZK4,256MB + 256MB,SC#0
NGDIMM#4 part# 501-5030-03 serial# L26ZKH,256MB + 256MB,SC#0
NGDIMM#5 part# 501-5030-03 serial# L2719Y,256MB + 256MB,SC#0
NGDIMM#6 part# 501-5030-03 serial# L26ZG3,256MB + 256MB,SC#0
NGDIMM#7 part# 501-5030-03 serial# L11GSB,256MB + 256MB,SC#0
Probing CMP2 memory configuration
NGDIMM#0 part# 501-7385-01 serial# A235EF,256MB + 256MB,SC#0
NGDIMM#1 part# 501-7385-01 serial# A1D644,256MB + 256MB,SC#0
NGDIMM#2 part# 501-7385-01 serial# A1D640,256MB + 256MB,SC#0
NGDIMM#3 part# 501-7385-01 serial# A1D4E7,256MB + 256MB,SC#0
NGDIMM#4 part# 501-7385-01 serial# A1D4D0,256MB + 256MB,SC#0
NGDIMM#5 part# 501-7385-01 serial# A235FE,256MB + 256MB,SC#0
NGDIMM#6 part# 501-7385-01 serial# A2010C,256MB + 256MB,SC#0
NGDIMM#7 part# 501-7385-01 serial# A1D677,256MB + 256MB,SC#0
Probing CMP3 memory configuration
NGDIMM#0 part# 501-5030-03 serial# L26ZK9,256MB + 256MB,SC#0
NGDIMM#1 part# 501-5030-03 serial# L26ZHT,256MB + 256MB,SC#0
NGDIMM#2 part# 501-5030-03 serial# L26ZKD,256MB + 256MB,SC#0
NGDIMM#3 part# 501-5030-03 serial# L26ZJH,256MB + 256MB,SC#0
NGDIMM#4 part# 501-5030-03 serial# L26ZJ6,256MB + 256MB,SC#0
NGDIMM#5 part# 501-5030-03 serial# L26ZG5,256MB + 256MB,SC#0
NGDIMM#6 part# 501-5030-03 serial# L26ZK2,256MB + 256MB,SC#0
NGDIMM#7 part# 501-5030-03 serial# L26ZKE,256MB + 256MB,SC#0 Done
Initializing CPUs.........
Mungeing Memory...........Done
HiMem: 0000.00b0.0000.0000, size: 0000.0002.0000.0000
Configuring Memory........ CMP0 CMP1 CMP2 CMP3 Done
Init ICache/etc........... CMP0 CMP1 CMP2 CMP3 Done
Init ECache Tags.......... CMP0 CMP1 CMP2 CMP3 Done
Clearing TLBs............. CMP0 CMP1 CMP2 CMP3 Done
Setup I/DTLBs............. CMP0 CMP1 CMP2 CMP3 Done
Enabling Cache/MMUs....... CMP0 CMP1 CMP2 CMP3 Done
Init ECache Data.......... CMP0 CMP1 CMP2 CMP3 Done
Initializing boot memory..
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 128KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.d0c2.2518;ROM CRC = 0000.0000.d0c2.2518
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.ee10 (508KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0 Done
BootCPU3 starting Forth at 0000.0000.f000.00e0
Diagnostic console initialized
Configure root name: SUNW,Sun-Fire-V490
SUNW,Sun-Fire-V490 Probing system devices
(1350 MHz @ 9:1, 1 MB) /: gptwo at 0,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 1,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 2,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 3,0 cmp cpu cpu memory-controller
/: gptwo at 4,0 Nothing there
/: gptwo at 5,0 Nothing there
/: gptwo at 6,0 Nothing there
/: gptwo at 7,0 Nothing there
/: gptwo at 8,0 pci pci
/: gptwo at 9,0 pci pci
Loading Support Packages: obp-tftp kbd-translator SUNW,i2c-ram-device SUNW,fru-device
Loading onboard drivers: ebus
/pci@9,700000/ebus@1: flashprom bbc power i2c i2c rtc gpio pmc rsc-control rsc-console serial
/pci@9,700000/ebus@1/i2c@1,2e: fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru nvram idprom fru fru
/pci@9,700000/ebus@1/i2c@1,30: temperature temperature temperature ioexp ioexp ioexp temperature ioexp ioexp ioexp ioexp temperature-sensor fru fru fru fru fru rscrtc
Memory Configuration:
/memory: CMP0 Bank0256 +256 +256 +256 : 1 GB @a0000000008-way #0
/memory: CMP0 Bank1256 +256 +256 +256 : 1 GB @a0000000008-way #2
/memory: CMP0 Bank2256 +256 +256 +256 : 1 GB @a0000000008-way #4
/memory: CMP0 Bank3256 +256 +256 +256 : 1 GB @a0000000008-way #6
/memory: CMP1 Bank0256 +256 +256 +256 : 1 GB @b0000000008-way #0
/memory: CMP1 Bank1256 +256 +256 +256 : 1 GB @b0000000008-way #2
/memory: CMP1 Bank2256 +256 +256 +256 : 1 GB @b0000000008-way #4
/memory: CMP1 Bank3256 +256 +256 +256 : 1 GB @b0000000008-way #6
/memory: CMP2 Bank0256 +256 +256 +256 : 1 GB @a0000000008-way #1
/memory: CMP2 Bank1256 +256 +256 +256 : 1 GB @a0000000008-way #3
/memory: CMP2 Bank2256 +256 +256 +256 : 1 GB @a0000000008-way #5
/memory: CMP2 Bank3256 +256 +256 +256 : 1 GB @a0000000008-way #7
/memory: CMP3 Bank0256 +256 +256 +256 : 1 GB @b0000000008-way #1
/memory: CMP3 Bank1256 +256 +256 +256 : 1 GB @b0000000008-way #3
/memory: CMP3 Bank2256 +256 +256 +256 : 1 GB @b0000000008-way #5
/memory: CMP3 Bank3256 +256 +256 +256 : 1 GB @b0000000008-way #7
Probing I/O buses
/pci@8,600000: Device 1 SUNW,qlc fp disk SUNW,qlc fp disk
/pci@8,600000: Device 2 Nothing there
/pci@8,700000: Device 2 SUNW,XVR-100
/pci@8,700000: Device 3 Nothing there
/pci@8,700000: Device 4 Nothing there
/pci@8,700000: Device 5 pci1214,334a
/pci@8,700000: Device 6 ide disk cdrom
/pci@9,600000: Device 1 network
/pci@9,600000: Device 2 SUNW,qlc fp disk
/pci@9,700000: Device 1 usb mouse hub keyboard
/pci@9,700000: Device 2 network
Sun Fire V490, Keyboard Present
Copyright 2007 Sun Microsystems, Inc.All rights reserved.
OpenBoot 4.22.34, 16384 MB memory installed, Serial #71389366.
Ethernet address 0:14:4f:41:50:b6, Host ID: 844150b6.
Creating CMP memory layout properties.
Running diagnostic script obdiag/normal
Testing /pci@9,600000/SUNW,qlc@2
Subtest pci-config-regs-tests
Subtest pci-registers-walk1
Subtest test-mbox-reg
Subtest test-risc-ram
Subtest mats-test
>> Testing RISC RAM (this may take a while)..........
Subtest loop-tests
>> Firmware copied
>> Waiting for loop to come up.
>> Waiting for firmware ready state
Subtest loop-tests:lip-test
Subtest loop-tests:lip-map-test
>> FCAL device count = 0x3
>> Found device with loop ID 0x7d (AL_PA = 0x1 )
>> Found device with loop ID 0x0 (AL_PA = 0xef )
>> Found device with loop ID 0x1 (AL_PA = 0xe8 )
Subtest loop-tests:inquiry-test
>> ISP2200 found at loop ID 0x7d
Subtest loop-tests:inquiry-test:disk-test
>> Direct-access device ( disk 0 ) found at loop ID 0x0
>> Waiting for disk to spin up (timeout in one minute)... Disk spun up.
>> Disk media test not run.
>> To run test, include "media" in test-args string.
Subtest loop-tests:inquiry-test:disk-test
>> Direct-access device ( disk 1 ) found at loop ID 0x1
>> Waiting for disk to spin up (timeout in one minute)... Disk spun up.
>> Disk media test not run.
>> To run test, include "media" in test-args string.
Testing /pci@9,700000/ebus@1/i2c@1,2e
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,a0
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,a2
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,a4
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,a6
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,a8
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,aa
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,ac
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@0,ae
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,a0
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,a2
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,a4
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,a6
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,a8
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,aa
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,ac
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@1,ae
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,a0
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,a2
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,a4
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,a6
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,a8
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,aa
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,ac
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@2,ae
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,a0
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,a2
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,a4
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,a6
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,a8
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,aa
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,ac
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@3,ae
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@4,a0
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@4,a2
Testing /pci@9,700000/ebus@1/i2c@1,2e/nvram@4,a4
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@4,a8
Testing /pci@9,700000/ebus@1/i2c@1,2e/fru@4,aa
Testing /pci@9,700000/ebus@1/i2c@1,30
Testing /pci@9,700000/ebus@1/i2c@1,30/temperature@0,30
>> External die temperature = 59
Testing /pci@9,700000/ebus@1/i2c@1,30/temperature@0,32
>> External die temperature = 63
Testing /pci@9,700000/ebus@1/i2c@1,30/temperature@0,34
>> External die temperature = 61
Testing /pci@9,700000/ebus@1/i2c@1,30/ioexp@0,44
Testing /pci@9,700000/ebus@1/i2c@1,30/ioexp@0,46
Testing /pci@9,700000/ebus@1/i2c@1,30/ioexp@0,4c
Testing /pci@9,700000/ebus@1/i2c@1,30/temperature@0,52
>> External die temperature = 62
Testing /pci@9,700000/ebus@1/i2c@1,30/ioexp@0,70
Testing /pci@9,700000/ebus@1/i2c@1,30/ioexp@0,72
Testing /pci@9,700000/ebus@1/i2c@1,30/fru@0,a0
Testing /pci@9,700000/ebus@1/i2c@1,30/fru@0,a2
Testing /pci@9,700000/ebus@1/i2c@1,30/fru@0,a6
Testing /pci@9,700000/ebus@1/i2c@1,30/fru@0,a8
Testing /pci@9,700000/ebus@1/i2c@1,30/fru@0,ae
Testing /pci@9,700000/ebus@1/bbc@1,0
Subtest bbc-aid-reg-test
Subtest bbc-arb-reg-test
Subtest bbc-jtag-cmd-reg-test
Subtest bbc-jtag-control-reg-test
Subtest bbc-i2c-bus-sel-reg-test
Subtest bbc-key-beep-ctrl-reg-test
Testing /pci@9,700000/ebus@1
Subtest vendor-id-test
Subtest device-id-test
Subtest mixmode-read
Subtest e2-class-test
Subtest status-reg-walk1
Subtest line-size-walk1
Subtest latency-walk1
Subtest line-walk1
Subtest dma-reg-test
Subtest dma-func-test
Subtest tcr-reg-test
Subtest flauxio-reg-test
Subtest modauxio-reg-test
Testing /pci@9,600000/network@1
Subtest reset-tests
Subtest reg-tests
Subtest mltpkt-gmii-int-lpb-test
>> MAC programmed to operate in internal loopback mode.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
Subtest phy-loopback-tests
>> Setting up PHY to operate at 10Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Setting up PHY to operate at 100Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Setting up PHY to operate at 1000Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
NOTE: External loopback tests are not run.
Include "loopback" in test-args and connect an
RJ-45 termination connector to ethernet ports.
Testing /pci@9,700000/network@2
Subtest reset-tests
Subtest reg-tests
Subtest mltpkt-gmii-int-lpb-test
>> MAC programmed to operate in internal loopback mode.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
Subtest phy-loopback-tests
>> Setting up PHY to operate at 10Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Setting up PHY to operate at 100Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Setting up PHY to operate at 1000Mbits/second.
>> Ethernet device set up to perform loopback at PHY device.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
>> Loopback buffer checked out okay.
NOTE: External loopback tests are not run.
Include "loopback" in test-args and connect an
RJ-45 termination connector to ethernet ports.
Testing /pci@9,700000/usb@1,3
Subtest usb-pci-reg-test
Subtest usb-ohci-hccnt-sft-rst-test
>> The USB host controller is in suspended state
Subtest usb-ohci-cnt-reg-test
Subtest usb-ohci-cmdsta-reg-test
Subtest usb-ohci-intsta-reg-test
Subtest usb-ohci-intena-reg-walk1
Subtest usb-ohci-hccntapt-reg-test
Subtest usb-ohci-prdcur-reg-res-test
Subtest usb-ohci-cnt-hd-reg-test
Subtest usb-ohci-cnt-cur-reg-test
Subtest usb-ohci-blk-hd-reg-test
Subtest usb-ohci-blk-cur-reg-test
Subtest usb-ohci-done-hd-reg-res-test
Subtest usb-ohci-frm-int-reg-test
Subtest usb-ohci-frm-num-reg-test
Subtest usb-ohci-prd-strt-reg-test
Subtest usb-ohci-prd-strt-reg-walk1
Subtest usb-ohci-lspd-thre-reg-test
Subtest usb-ohci-rhb-desca-reg-test
Subtest usb-ohci-rhb-descb-reg-test
Testing /pci@9,700000/ebus@1/pmc@1,300700
Subtest pmc-d&i-reg-test
Subtest pmc-fer1-reg-test
PM Function Enable Register 1 returns ff
Subtest pmc-fer2-reg-test
PM Function Enable Register 2 returns 87
Subtest pmc-pmc1-reg-test
PM Power Management Control 1 returns 0
Subtest pmc-pmc2-reg-test
PM Power Management Control 2 returns 87
Subtest pmc-pmc3-reg-test
PM Power Management Control 3 returns e
Subtest pmc-wdto-reg-test
PM WatchDog Timeout returns 0
Subtest pmc-wdcf-reg-test
PM WatchDog Configuration returns 0
Subtest pmc-wdst-reg-test
PM WatchDog Status returns 1
Subtest pmc-ebal-reg-test
PM Event Base Address Low returns 10
Subtest pmc-ebah-reg-test
PM Event Base Address High returns 7
Subtest pmc-tbal-reg-test
PM Timer Base Address Low returns 14
Subtest pmc-tbah-reg-test
PM Timer Base Address High returns 7
Subtest pmc-cbal-reg-test
PM Control Base ADdress Low returns 14
Subtest pmc-cbah-reg-test
PM Control Base Address High returns 7
Subtest pmc-gbal-reg-test
PM Gen Purpose Stat Base Adr Low returns 20
Subtest pmc-gbah-reg-test
PM Gen Purpose Stat Base Adr High returns 7
Testing /pci@9,700000/ebus@1/rtc@1,300070
Subtest rtc-cra-walk1
Subtest rtc-crb-walk1
Subtest rtc-pi-test
>> PeriodicInterrupt, Enabled
>> Periodic Interrupt Rate changed from: NONEto: NONE
>> Testing to determine if PF will remain disabled...
>> PeriodicInterruptFlag (PF), rate NONE, test passed...
>> The loop-counter was... 600000
>> Testing to determing if PF will enable at different PI rates...
>> Periodic Interrupt Rate changed from: NONEto: 3.90625 msec
>> Periodic Interrupt Rate changed from: 3.90625 msecto: 7.1825 msec
>> Periodic Interrupt Rate changed from: 7.1825 msecto: 122.070 usec
>> Periodic Interrupt Rate changed from: 122.070 usecto: 244.141 usec
>> Periodic Interrupt Rate changed from: 244.141 usecto: 488.281 usec
>> Periodic Interrupt Rate changed from: 488.281 usecto: 976.562 usec
>> Periodic Interrupt Rate changed from: 976.562 usecto: 1.953125 msec
>> Periodic Interrupt Rate changed from: 1.953125 msecto: 3.90625 msec
>> Periodic Interrupt Rate changed from: 3.90625 msecto: 7.1825 msec
>> Periodic Interrupt Rate changed from: 7.1825 msecto: 15.625 msec
>> Periodic Interrupt Rate changed from: 15.625 msecto: 31.25 msec
>> Periodic Interrupt Rate changed from: 31.25 msecto: 62.5 msec
>> Periodic Interrupt Rate changed from: 62.5 msecto: 125 msec
>> Periodic Interrupt Rate changed from: 125 msecto: 250 msec
>> Periodic Interrupt Rate changed from: 250 msecto: 500 msec
>> Periodic Interrupt Rate changed from: 500 msecto: NONE
Subtest sio-rtc-af-test
>> Looping until RTCC-AF detects Alarm event...
>> AlarmInterruptFlag (AF) test passed...
Subtest sio-rtc-afirqf-test
>> AlarmInterrupt, Enabled
>> Looping until AF detects Alarm event and IRQF becomes active...
>> InterruptRequestFlag (AF+IRQF) test passed...
Subtest rtc-ufirqf-test
>> Update-Ended Interrupt Flag (UF) detected, test passed...
>> InterruptRequestFlag detected (IRQF) with UIE disabled.
>> UF+IRQF (UIE:enabled), test passed...
Subtest apc-apcr1-reg-test
>> APC Power Failure DetectBit OK.
>> APC !POR Test, attempting to select Level !POR
>> APC Level !POR selected successfully, attempting to deactivate.
>> APC !POR output signal has now been deactivated.
Subtest rtc-ds-test
>> Daylight Savings: Disabled
>> Daylight Savings disabled, April test, passed.
>> Daylight Savings disabled, October test, passed.
RTC rollover test passed.
System is operating in Service Mode.
Initializing 12MB of memory at addr b1ff000000 -
Initializing8176MB of memory at addr b000000000 -
Initializing 8GB of memory at addr a000000000 \|/-\|/-\|/-\|/-
Reading temperature limits from FRUPROMs: CMP0/2 CMP1/3 BACKPLANE
Environmental monitor is ON
Aborting auto-boot sequence.
{3} ok B boot disk
Resetting ...
<*>
Firmware I/O Diagnostics Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online:CMP0 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP1 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP2 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online: *CMP3 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Enabling system bus....... CMP0 CMP1 CMP2 CMP3 Done
Initializing CPUs.........
Init ICache/etc........... CMP0 CMP1 CMP2 CMP3 Done
Init ECache Tags.......... CMP0 CMP1 CMP2 CMP3 Done
Clearing TLBs............. CMP0 CMP1 CMP2 CMP3 Done
Setup I/DTLBs............. CMP0 CMP1 CMP2 CMP3 Done
Enabling Cache/MMUs....... CMP0 CMP1 CMP2 CMP3 Done
Init ECache Data.......... CMP0 CMP1 CMP2 CMP3 Done
Initializing boot memory..
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 128KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.d0c2.2518;ROM CRC = 0000.0000.d0c2.2518
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.ee10 (508KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0 Done
BootCPU3 starting Forth at 0000.0000.f000.00e0
Diagnostic console initialized
Configure root name: SUNW,Sun-Fire-V490
SUNW,Sun-Fire-V490 Probing system devices
(1350 MHz @ 9:1, 1 MB) /: gptwo at 0,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 1,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 2,0 cmp cpu cpu memory-controller
(1350 MHz @ 9:1, 1 MB) /: gptwo at 3,0 cmp cpu cpu memory-controller
/: gptwo at 4,0 Nothing there
/: gptwo at 5,0 Nothing there
/: gptwo at 6,0 Nothing there
/: gptwo at 7,0 Nothing there
/: gptwo at 8,0 pci pci
/: gptwo at 9,0 pci pci
Loading Support Packages: obp-tftp kbd-translator SUNW,i2c-ram-device SUNW,fru-device
Loading onboard drivers: ebus
/pci@9,700000/ebus@1: flashprom bbc power i2c i2c rtc gpio pmc rsc-control rsc-console serial
/pci@9,700000/ebus@1/i2c@1,2e: fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru nvram idprom fru fru
/pci@9,700000/ebus@1/i2c@1,30: temperature temperature temperature ioexp ioexp ioexp temperature ioexp ioexp ioexp ioexp temperature-sensor fru fru fru fru fru rscrtc
Memory Configuration:
/memory: CMP0 Bank0256 +256 +256 +256 : 1 GB @a0000000008-way #0
/memory: CMP0 Bank1256 +256 +256 +256 : 1 GB @a0000000008-way #2
/memory: CMP0 Bank2256 +256 +256 +256 : 1 GB @a0000000008-way #4
/memory: CMP0 Bank3256 +256 +256 +256 : 1 GB @a0000000008-way #6
/memory: CMP1 Bank0256 +256 +256 +256 : 1 GB @b0000000008-way #0
/memory: CMP1 Bank1256 +256 +256 +256 : 1 GB @b0000000008-way #2
/memory: CMP1 Bank2256 +256 +256 +256 : 1 GB @b0000000008-way #4
/memory: CMP1 Bank3256 +256 +256 +256 : 1 GB @b0000000008-way #6
/memory: CMP2 Bank0256 +256 +256 +256 : 1 GB @a0000000008-way #1
/memory: CMP2 Bank1256 +256 +256 +256 : 1 GB @a0000000008-way #3
/memory: CMP2 Bank2256 +256 +256 +256 : 1 GB @a0000000008-way #5
/memory: CMP2 Bank3256 +256 +256 +256 : 1 GB @a0000000008-way #7
/memory: CMP3 Bank0256 +256 +256 +256 : 1 GB @b0000000008-way #1
/memory: CMP3 Bank1256 +256 +256 +256 : 1 GB @b0000000008-way #3
/memory: CMP3 Bank2256 +256 +256 +256 : 1 GB @b0000000008-way #5
/memory: CMP3 Bank3256 +256 +256 +256 : 1 GB @b0000000008-way #7
Probing I/O buses
/pci@8,600000: Device 1 SUNW,qlc fp disk SUNW,qlc fp disk
/pci@8,600000: Device 2 Nothing there
/pci@8,700000: Device 2 SUNW,XVR-100
/pci@8,700000: Device 3 Nothing there
/pci@8,700000: Device 4 Nothing there
/pci@8,700000: Device 5 pci1214,334a
/pci@8,700000: Device 6 ide disk cdrom
/pci@9,600000: Device 1 network
/pci@9,600000: Device 2 SUNW,qlc fp disk
/pci@9,700000: Device 1 usb mouse hub keyboard
/pci@9,700000: Device 2 network
Sun Fire V490, Keyboard Present
Copyright 2007 Sun Microsystems, Inc.All rights reserved.
OpenBoot 4.22.34, 16384 MB memory installed, Serial #71389366.
Ethernet address 0:14:4f:41:50:b6, Host ID: 844150b6.
Creating CMP memory layout properties.
System is operating in Service Mode.
Initializing 12MB of memory at addr b1ff000000 -
Initializing8176MB of memory at addr b000000000 -
Initializing 8GB of memory at addr a000000000 \|/-\|/-\|/-\|/-
Reading temperature limits from FRUPROMs: CMP0/2 CMP1/3 BACKPLANE
Environmental monitor is ON
Rebooting with command: boot disk
Boot device: /pci@9,600000/SUNW,qlc@2/fp@0,0/disk@0,0File and args:
ufs-file-system
Loading: /platform/SUNW,Sun-Fire-V490/boot_archive
Loading: /platform/sun4u/boot_archive
|
ramdisk-root hsfs-file-system
Loading: /platform/SUNW,Sun-Fire-V490/kernel/sparcv9/unix
Loading: /platform/sun4u/kernel/sparcv9/unix
|/-\|/-\|/-\|/-\|/-\|
SunOS Release 5.10 Version Generic_137137-09 64-bit
Copyright 1983-2008 Sun Microsystems, Inc.All rights reserved.
Use is subject to license terms.
/-os-io \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|//kernel/fs/sparcv9/mntfs: undefined symbol 'vfs_mono_time'
WARNING: mod_load: cannot load module 'mntfs'
WARNING: Cannot mount /etc/mnttab
/kernel/fs/sparcv9/tmpfs: undefined symbol 'uio_prefaultpages'
WARNING: mod_load: cannot load module 'tmpfs'
WARNING: Cannot mount /etc/svc/volatile
/kernel/fs/sparcv9/sharefs: undefined symbol 'pkp_tab_hash'
WARNING: mod_load: cannot load module 'sharefs'
WARNING: Cannot mount /etc/dfs/sharetab
/kernel/strmod/sparcv9/rpcmod: undefined symbol 'rpc_gss_get_service_type'
WARNING: mod_load: cannot load module 'rpcmod'
/kernel/drv/sparcv9/md: undefined symbol 'zone_get_hostid'
/kernel/drv/sparcv9/md: undefined symbol 'xdr_rpcb'
/kernel/drv/sparcv9/md: undefined symbol 'rpc_uaddr2port'
WARNING: mod_load: cannot load module 'md'
WARNING: md: unable to resolve dependency, module 'strmod/rpcmod' not found
Cannot assemble drivers for root /pseudo/md@0:0,11,blk
Cannot remount root on /pseudo/md@0:0,11,blk fstype ufs
panic/thread=180e000: vfs_mountroot: cannot remount root
000000000180b950 genunix:vfs_mountroot+380 (21, 2000, 189fa90, 187b7d0, 1875c00, 18761e0)
%l0-3: 0000000000000001 0000000000008025 000006002187aa80 000000000125cc00
%l4-7: 0000000001875f98 000006002187aa80 000000000189fa90 0000000000002021
000000000180ba10 genunix:main+a0 (1815180, 180c000, 1839750, 18c6c00, 181b580, 1815000)
%l0-3: 0000000001015400 0000000000000001 0000000070002000 0000000000000000
%l4-7: 000000000183ec00 0000000000000003 000000000180c000 0000000000000000
syncing file systems... done
skipping system dump - no dump device configured
rebooting...
Resetting ...
<*>
Software Reset
@(#)OBP 4.22.34 2007/07/23 13:01 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online:CMP0 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP1 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online:CMP2 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Online: *CMP3 UltraSPARC IV(v3.1)9:1 1350MHz8MB 5:1 ECache
Executing POST w/%o0 = 0000.1000.0101.4003
0:0>
0:0>@(#)Sun Fire V480/V490 POST 4.22.34 2007/07/23 13:12
/export/delivery/delivery/4.22/4.22.34/post4.22.x/Camelot/cstone/integrated(root)
0:0>Copyright 2007 Sun Microsystems, Inc. All rights reserved
0:0>Jump from OBP->POST.
0:0>diag-switch? configuration variable set TRUE.
0:0>Keyswitch in DIAGNOSTIC POSITION.
0:0>Diag level set to MAX.
0:0>Verbosity level set to MAX.
0:0>MFG scrpt mode set NORM
0:0>I/O port set to serial TTYA.
0:0>
0:0>Start selftest... 本帖最后由 346279055 于 2012-04-12 20:29 编辑
thread=180e000: vfs_mountroot: cannot remount root
你的系统有问题吧。
系统盘别插错槽位 没有的，磁盘在做完系统后就没动过的 POST Passed all devices
硬件没有问题，是根盘出问题了，从disk1引导，重新对根盘镜像吧。 thanks
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