如何判断cpu板急

wjxlcc 发表于 2012-05-28 17:39

不知道哪个cpu板有问题求大虾指点如何判断
0:0>
0:0>@(#) Sun Fire V880/V890 POST 4.18.11 2006/05/03 07:51
   /export/delivery/delivery/4.18/4.18.11/post4.18.0/Camelot/daktari/integrated(root)
0:0>Copyright 2006 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>Diag level set to MIN.
0:0>Verbosity level set to NORMAL.
0:0>
0:0>Start selftest...
0:0>CPUs present in system: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0

******POST Running ******

0:0>Test CPU(s)....-
******POST Running ******

Done
0:0>Init Scan/I2C....Done
0:0>Basic Memory Test....\
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 0 Dimm 1, J2901 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 0 DIMM 1 Pin 194
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 0 Dimm 1, J2901 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 0 DIMM 1 Pin 150
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 0 Dimm 2, J3001 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 0 DIMM 2 Pin 190
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 0 Dimm 3, J3000 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 0 DIMM 3 Pin 195
0:0>END_ERROR

|
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 1 Dimm 1, J3101 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 1 DIMM 1 Pin 14
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 1 Dimm 2, J3201 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 1 DIMM 2 Pin 210
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 1 Dimm 2, J3201 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 1 DIMM 2 Pin 190
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 1 Dimm 3, J3200 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 1 DIMM 3 Pin 194
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 1 Dimm 3, J3200 side 1
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 1 DIMM 3 Pin 224
0:0>END_ERROR

/
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 2 Dimm 1, J2901 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 2 DIMM 1 Pin 194
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 2 Dimm 1, J2901 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 2 DIMM 1 Pin 150
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 2 Dimm 2, J3001 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 2 DIMM 2 Pin 190
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 2 Dimm 3, J3000 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 2 DIMM 3 Pin 195
0:0>END_ERROR

-
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 1, J3101 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 3 DIMM 1 Pin 14
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 2, J3201 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 3 DIMM 2 Pin 210
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 2, J3201 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 3 DIMM 2 Pin 190
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 3, J3200 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 3 DIMM 3 Pin 194
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 3, J3200 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = DIMM failure Bank 3 DIMM 3 Pin 224
0:0>END_ERROR

\
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0 Bank 3 Dimm 3, J3200 side 2
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = No Memory Detected
0:0>END_ERROR

|
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG =
      *** Test Failed!! ***

0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG =

   ERROR:1 AFSR Error 00100004.00000140, AFSR_EXT Error 00000000.00000000, AFAR 00000003.00000000.

0:0>END_ERROR

/
0:0>WARNING: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>MSG =             AFSR error after running test Probe and Setup Memory.
0:0>END_WARNING

0:0>
0:0>ERROR: TEST = Probe and Setup Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = ERROR:    Memory error on master CPU, rolling over to new master.
0:0>END_ERROR

-
1:0>Start selftest...
1:0>CPUs present in system: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0
1:0>Test CPU(s)....Done
1:0>Init Scan/I2C....Done
1:0>Basic Memory Test....-
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 0 Dimm 0, J7900 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 0 DIMM 0 Pin 199
2:0>END_ERROR

\
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 0 Dimm 0, J7900 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 0 DIMM 0 Pin 189
2:0>END_ERROR

/
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 0 Dimm 1, J7901 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 0 DIMM 1 Pin 82
2:0>END_ERROR

|
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 0 Dimm 3, J8000 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 0 DIMM 3 Pin 149
2:0>END_ERROR

\
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 1 Dimm 2, J8201 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 1 DIMM 2 Pin 82
2:0>END_ERROR

/
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 1 Dimm 2, J8201 side 1
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 1 DIMM 2 Pin 107
2:0>END_ERROR

-
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 2 Dimm 0, J7900 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 2 DIMM 0 Pin 199
2:0>END_ERROR

|
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 2 Dimm 0, J7900 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 2 DIMM 0 Pin 189
2:0>END_ERROR

-
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 2 Dimm 1, J7901 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 2 DIMM 1 Pin 82
2:0>END_ERROR

-
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 2 Dimm 3, J8000 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 2 DIMM 3 Pin 149
2:0>END_ERROR

/
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 3 Dimm 2, J8201 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 3 DIMM 2 Pin 82
2:0>END_ERROR

-
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2 Bank 3 Dimm 2, J8201 side 2
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = DIMM failure Bank 3 DIMM 2 Pin 107
2:0>END_ERROR

/
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG =

   ERROR:1 AFSR Error 00300004.0000003a, AFSR_EXT Error 00000000.00000000, AFAR 00000023.00000020.

2:0>END_ERROR

\
2:0>WARNING: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>MSG =             AFSR error after running test Probe and Setup Memory.
2:0>END_WARNING

/
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
   Trap Type    00000000.00000063
   Trap PC    ffffffff.f0125084
   Trap Level 00000000.00000001
   AFSR       00100002.00000178
   AFAR       00000030.001b0020
1:0>END_WARNING

|
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 1, J7901 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 0 DIMM 1 Pin 13
1:0>END_ERROR

-
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 1, J7901 side 1
1:0>MSG = Data or Instruction Access Error,
   Trap Type    00000000.00000063
   Trap PC    ffffffff.f0125084
   Trap Level 00000000.00000001
   AFSR       00100002.00000178
   AFAR       00000032.001b0020
1:0>END_WARNING

/
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 1, J7901 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 2 DIMM 1 Pin 13
1:0>END_ERROR

/
1:0>WARNING: TEST = Data Bitwalk on Slave 6
1:0>H/W under test = CPU6, All CPU6 Memory
1:0>MSG = Data or Instruction Access Error,
   Trap Type    00000000.00000063
   Trap PC    ffffffff.f0125084
   Trap Level 00000000.00000001
   AFSR       00100002.000001b4
   AFAR       00000061.001b0020
1:0>END_WARNING

|
1:0>ERROR: TEST = Data Bitwalk on Slave 6
1:0>H/W under test = CPU6 Bank 1 Dimm 3, J8200 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 1 DIMM 3 Pin 193
1:0>END_ERROR

-
1:0>WARNING: TEST = Data Bitwalk on Slave 6
1:0>H/W under test = CPU6 Bank 1 Dimm 3, J8200 side 1
1:0>MSG = Data or Instruction Access Error,
   Trap Type    00000000.00000063
   Trap PC    ffffffff.f0125084
   Trap Level 00000000.00000001
   AFSR       00100002.000001b4
   AFAR       00000063.001b0020
1:0>END_WARNING

/
1:0>ERROR: TEST = Data Bitwalk on Slave 6
1:0>H/W under test = CPU6 Bank 3 Dimm 3, J8200 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 3 DIMM 3 Pin 193
1:0>END_ERROR

-
3:0>ERROR: TEST = Check Mem Banks
3:0>H/W under test = CPU, Motherboard/Centerplane, I/O board, (system init)
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = Offline Bank 0.
3:0>END_ERROR

|
6:0>ERROR: TEST = Check Mem Banks
6:0>H/W under test = CPU, Motherboard/Centerplane, I/O board, (system init)
6:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
6:0>MSG = Offline Bank 1.
6:0>END_ERROR

-
3:0>ERROR: TEST = Check Mem Banks
3:0>H/W under test = CPU, Motherboard/Centerplane, I/O board, (system init)
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = Offline Bank 2.
3:0>END_ERROR

6:0>
6:0>ERROR: TEST = Check Mem Banks
6:0>H/W under test = CPU, Motherboard/Centerplane, I/O board, (system init)
6:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
6:0>MSG = Offline Bank 3.
6:0>END_ERROR

Done
1:0>Memory Block....Done
1:0>IO-Bridge Tests...|Done
1:0>Enable Errors....Done
1:0>ERROR:
1:0> POST toplevel status has the following failures:
1:0>          CPU0 Memory Bank 0
1:0>          CPU0 Memory Bank 1
1:0>          CPU0 Memory Bank 2
1:0>          CPU0 Memory Bank 3
1:0>          CPU2 Memory Bank 0
1:0>          CPU2 Memory Bank 1
1:0>          CPU2 Memory Bank 2
1:0>          CPU2 Memory Bank 3
1:0>          CPU3 Memory Bank 0
1:0>          CPU3 Memory Bank 2
1:0>          CPU6 Memory Bank 1
1:0>          CPU6 Memory Bank 3
1:0> POST failed the following devices on CPU 0:
1:0>          Mem Bank0 DIMM1
1:0>          Mem Bank0 DIMM2
1:0>          Mem Bank0 DIMM3
1:0>          Mem Bank1 DIMM1
1:0>          Mem Bank1 DIMM2
1:0>          Mem Bank1 DIMM3
1:0>          Mem Bank2 DIMM1
1:0>          Mem Bank2 DIMM2
1:0>          Mem Bank2 DIMM3
1:0>          Mem Bank3 DIMM1
1:0>          Mem Bank3 DIMM2
1:0>          Mem Bank3 DIMM3
1:0> POST failed the following devices on CPU 2:
1:0>          Mem Bank0 DIMM0
1:0>          Mem Bank0 DIMM1
1:0>          Mem Bank0 DIMM3
1:0>          Mem Bank1 DIMM2
1:0>          Mem Bank2 DIMM0
1:0>          Mem Bank2 DIMM1
1:0>          Mem Bank2 DIMM3
1:0>          Mem Bank3 DIMM2
1:0> POST failed the following devices on CPU 3:
1:0>          Mem Bank0 DIMM1
1:0>          Mem Bank2 DIMM1
1:0> POST failed the following devices on CPU 6:
1:0>          Mem Bank1 DIMM3
1:0>          Mem Bank3 DIMM3
1:0>END_ERROR

1:0>POST:    Return to OBP.
POST Reset

Enabling system bus....... Done
Probing Memory............ Done
Initializing CPUs......... Done
Initializing boot memory.. Done
Initializing OpenBoot
Probing system devices
Probing I/O buses
screen not found.
keyboard not found.
Keyboard not present.Using ttya for input and output.
Probing system devices
Probing I/O buses

Sun Fire V890, No Keyboard
Copyright 2005 Sun Microsystems, Inc.All rights reserved.
OpenBoot 4.18.11, 20480 MB memory installed, Serial #82251638.
Ethernet address 0:14:4f:e7:f:76, Host ID: 84e70f76.

Running diagnostic script obdiag/normal

Testing /pci@8,600000/network@1
Testing /pci@8,600000/SUNW,qlc@2
Testing /pci@9,700000/ebus@1/i2c@1,2e
Testing /pci@9,700000/ebus@1/i2c@1,30
Testing /pci@9,700000/ebus@1/i2c@1,50002e
Testing /pci@9,700000/ebus@1/i2c@1,500030
Testing /pci@9,700000/ebus@1/bbc@1,0
Testing /pci@9,700000/ebus@1/bbc@1,500000
Testing /pci@8,700000/ide@1
Testing /pci@9,700000/network@1,1
Testing /pci@9,700000/usb@1,3
Testing /pci@9,700000/ebus@1/gpio@1,300600
Testing /pci@9,700000/ebus@1/pmc@1,300700
Testing /pci@9,700000/ebus@1/rtc@1,300070


ERROR: Power On Self Test Failed. Cause:
CPU2 Bank 0 Dimm 0, J7900 side 1
ERROR: POST failed.

Resetting ...

Enabling system bus....... Done
Initializing CPUs......... Done
Initializing boot memory.. Done
Initializing OpenBoot
Probing system devices
Probing I/O buses
screen not found.
keyboard not found.
Keyboard not present.Using ttya for input and output.
Probing system devices
Probing I/O buses

Sun Fire V890, No Keyboard
Copyright 2005 Sun Microsystems, Inc.All rights reserved.
OpenBoot 4.18.11, 20480 MB memory installed, Serial #82251638.
Ethernet address 0:14:4f:e7:f:76, Host ID: 84e70f76.


ERROR: Power On Self Test Failed. Cause:
CPU2 Bank 0 Dimm 0, J7900 side 1
ERROR: POST failed.
Rebooting with command: boot
Boot device: disk:aFile and args:
WARNING: Unexpected token '/' on line 82 of etc/system
SunOS Release 5.10 Version Generic_127127-11 64-bit
Copyright 1983-2008 Sun Microsystems, Inc.All rights reserved.
Use is subject to license terms.
Hostname: gmccnbi2o
NOTICE: realloccg /var: file system full
/dev/md/rdsk/d40 is clean
/dev/md/rdsk/d60 is clean
/dev/md/rdsk/d30 is clean
/dev/md/rdsk/d70 is clean
NOTICE: alloc: /var: file system full
NOTICE: alloc: /var: file system full

gmccnbi2o console login: syslogd: /var/adm/messages: No space left on device
May 22 16:01:57 gmccnbi2o savecore: not enough space in /var/crash/gmccnbi2o (4 MB avail, 1700 MB needed)
May 22 16:01:58 gmccnbi2o sendmail: My unqualified host name (gmccnbi2o) unknown; sleeping for retry
May 22 16:01:58 gmccnbi2o sendmail: My unqualified host name (gmccnbi2o) unknown; sleeping for retry
May 22 16:01:58 gmccnbi2o ufs: NOTICE: realloccg /var: file system full

gmccnbi2o console login: root
Password: May 22 16:02:20 gmccnbi2o ufs: NOTICE: alloc: /var: file system full

May 22 16:02:20 gmccnbi2o login: ROOT LOGIN /dev/console
Last login: Wed Dec 28 14:53:17 on console
Sun Microsystems Inc. SunOS 5.10    Generic January 2005
#
SUNW-MSG-ID: FMD-8000-2K, TYPE: Defect, VER: 1, SEVERITY: Minor
EVENT-TIME: Tue May 22 16:02:20 CST 2012
PLATFORM: SUNW,Sun-Fire-V890, CSN: -, HOSTNAME: gmccnbi2o
SOURCE: fmd-self-diagnosis, REV: 1.0
EVENT-ID: fd73d45a-6567-4735-fed0-f72da56305cc
DESC: A Solaris Fault Manager component has experienced an error that required the module to be disabled.Refer to http://sun.com/msg/FMD-8000-2K for more information.
AUTO-RESPONSE: The module has been disabled.Events destined for the module will be saved for manual diagnosis.
IMPACT: Automated diagnosis and response for subsequent events associated with this module will not occur.
REC-ACTION: Use fmdump -v -u <EVENT-ID> to locate the module.Use fmadm reset <module> to reset the module.

#
#

wjxlcc 发表于 2012-05-28 17:41

服务器sun v890

qianxia0_ 发表于 2012-05-29 10:49

内存报错了，更换内存吧CPU2 Bank 0 Dimm 0, J7900 side 1、CPU6 Bank 3 Dimm 3, J8200 side 2等等这些报了的

doging 发表于 2012-05-29 11:10

CPU2 Bank 0 Dimm 0, J7900 side 1

wjxlcc 发表于 2012-05-29 11:48

CPU2 Bank 0 Dimm 0, J7900 side 1 是什么意思在哪个cpu板上本人小白

8894106 发表于 2012-05-29 23:21

那么多条内存同时报错就不太可能是内存了。如果真是内存问题，难道机器跑了很久，平时都没人鸟它？

wjxlcc 发表于 2012-05-30 09:31

我想知道报错的内存在哪个cpu板上应该是cpu板的问题

znnnz 发表于 2012-05-30 11:13

V890的话：

CPU0和2位于插槽A；
CPU1和3位于插槽B；
CPU4和6位于插槽C；
CPU5和7位于插槽D。

wjxlcc 发表于 2012-05-30 12:34

哦太谢谢了受教了终于知道了

wjxlcc 发表于 2012-05-30 12:41

为什么CPU0和2位于插槽A；
为什么CPU1和3位于插槽B；
哪里可以知道呀

页: [1] 2

Chinaunix's Archiver

如何判断cpu板 急

如何判断cpu板急