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zhangyudong1987 发表于 2012-10-20 20:14

T3-1问题ALOM

本帖最后由 zhangyudong1987 于 2012-11-12 10:29 编辑

系统目前可以正常使用；系统状态为失败

这里面有记录prtdiag以及一些错误信息
-> start /SP/console
Are you sure you want to start /SP/console (y/n)? y

Serial console started.To stop, type #.

Oct 19 15:17:54 Solaris10 sshd: Failed keyboard-interactive for root from 223.254.105.8 port 2504 ssh2
Oct 19 15:17:56 Solaris10 last message repeated 1 time
Oct 19 15:17:57 Solaris10 sshd: Failed none for root from 223.254.105.8 port 2504 ssh2

-> show components
Target          | Property             | Value
--------------------+------------------------+---------------------------------
/SYS/MB/CMP0    | component_state    | Enabled
/SYS/MB/CMP0/BOB0/| component_state    | Enabled
CH0/D0          |                      |
/SYS/MB/CMP0/BOB0/| component_state    | Enabled
CH1/D0          |                      |
/SYS/MB/CMP0/BOB1/| component_state    | Enabled
CH0/D0          |                      |
/SYS/MB/CMP0/BOB1/| component_state    | Enabled
CH1/D0          |                      |
/SYS/MB/CMP0/BOB2/| component_state    | Enabled
CH0/D0          |                      |
/SYS/MB/CMP0/BOB2/| component_state    | Enabled
CH1/D0          |                      |
/SYS/MB/CMP0/BOB3/| component_state    | Enabled
CH0/D0          |                      |
/SYS/MB/CMP0/BOB3/| component_state    | Enabled
CH1/D0          |                      |
/SYS/MB/CMP0/L2T0 | component_state    | Enabled
/SYS/MB/CMP0/L2T1 | component_state    | Enabled
/SYS/MB/CMP0/L2T2 | component_state    | Enabled
/SYS/MB/CMP0/L2T3 | component_state    | Enabled
/SYS/MB/CMP0/L2T4 | component_state    | Enabled
/SYS/MB/CMP0/L2T5 | component_state    | Enabled
/SYS/MB/CMP0/L2T6 | component_state    | Enabled
/SYS/MB/CMP0/L2T7 | component_state    | Enabled
/SYS/MB/CMP0/CORE0| component_state    | Enabled
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE0/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE1| component_state    | Enabled
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE1/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE2| component_state    | Enabled
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE2/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE3| component_state    | Enabled
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE3/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE4| component_state    | Enabled
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE4/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE5| component_state    | Enabled
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE5/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE6| component_state    | Enabled
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE6/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE7| component_state    | Enabled
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE7/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE8| component_state    | Enabled
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE8/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/CORE9| component_state    | Enabled
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P0             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P1             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P2             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P3             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P4             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P5             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P6             |                      |
/SYS/MB/CMP0/CORE9/ | component_state    | Enabled
P7             |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10          |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P0       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P1       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P2       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P3       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P4       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P5       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P6       |                      |
/SYS/MB/CMP0/    | component_state    | Enabled
CORE10/P7       |                      |

DC_楚楚 发表于 2012-10-20 20:44

T3 不支持ALOM，只有T5XX0系列的ILOM才能创建ALOM。

DC_楚楚 发表于 2012-10-20 20:45

看一下你OK的参数

zhangyudong1987 发表于 2012-10-21 09:49

回复 2# DC_楚楚

如果不支持的话，那是不是说明不能进入SC模式吧。。。
那这几张图片里面的错误是什么意思？

nimysun 发表于 2012-10-21 10:48

在OS里面把ILOM刷到最新，

然后清除这个报错，

断电重启，看可否恢复。

如果还有报错的话，那么基本肯定肯定你有硬件问题了，需要收集ILOM snapshot给你的服务提供商检查了。

DC_楚楚 发表于 2012-10-21 12:47

如楼上，faulty很有可能只是误报:)

qianxia0_ 发表于 2012-10-22 09:06

你可以在sp下show faulty看看，也可以在系统下fmadm faulty看看具体是什么报错

zhangyudong1987 发表于 2012-10-22 11:49

回复 7# qianxia0_

系统下面fmadm faulty下面是空的，什么都没有，。。SP下面直接show faulty，这个到没试。。。

znnnz 发表于 2012-10-23 14:54

恢复出厂默认值

zhangyudong1987 发表于 2012-10-24 18:41

回复 9# znnnz

这样也行？

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