请教：SUN V880 CPU/Memory Slot LEDs "OK-to-Remove" 黄灯
本帖最后由 linton 于 2013-02-27 17:09 编辑SUN V880 CPU/Memory Slot LEDs "OK-to-Remove" 黄灯，显示器无任何显示，
机器前面板的“Attention Right Side”和“System Fault LED”黄灯。
如何查是CPU,内存，还是CPU板的问题？还是其他问题？
谢谢
自检信息：
<*>
Hardware Power On
@(#)OBP4.7.5 2003/01/08 11:36 Sun Fire 880
Front Panel Keyswitch is in Diagnostic position.
Online: CPU0 CPU2*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing MDR via JTAG...Done
Enabling DAR error circuitry...Done
Probing Motherboard....part# 501-6323-02 serial# 017270
Safari min 100MHz, cumulative 100MHz;max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Board......part# 501-5142-18 serial# 043616
Probing System RSC.....part# 501-5856-06 serial# 161689
Probing PwrDistBoard...part# 375-0071-03 serial# N36370
Probing PowerSupply0...part# 300-1353-02 serial# M12988
Probing PowerSupply1...part# 300-1353-02 serial# M12991
Probing PowerSupply2...part# 300-1353-02 serial# M12986
Probing GPTwo Slot A...part# 501-6334-03 serial# 097940
Safari min 100MHz, cumulative 100MHz;max 150MHz, cumulative 150MHz
CPU rated speed 900MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...No module detected
Probing GPTwo Slot C...No module detected
Probing GPTwo Slot D...No module detected
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU0 Rated Speed 900MHz, Safari 150MHz, want 6:1, got 6:1 ==> CPU 900MHz
Ecache 8MB 3.3ns mode=3-3-3 2-way ECCR: 0000.0000.0309.4400
... CPU2 Rated Speed 900MHz, Safari 150MHz, want 6:1, got 6:1 ==> CPU 900MHz
Ecache 8MB 3.3ns mode=3-3-3 2-way ECCR: 0000.0000.0309.4400 ...Done
Setting system speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP4.7.5 2003/01/08 11:36 Sun Fire 880
Front Panel Keyswitch is in Diagnostic position.
Online:CPU0 Ultra-III+ (v2.3) 6:1 900MHz 8MB 3:1 ECache
Online: *CPU2 Ultra-III+ (v2.3) 6:1 900MHz 8MB 3:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.2042
0>@(#) Daktari POST 4.7.4 2002/12/23 15:45
/dat/fw/work/staff/firmware_re/post/post-build-4.7.4/Camelot/daktari/inte
grated(firmware_re)
0>Jump from OBP->POST.
0>CPUs present in system: 0 2
0>Keyswitch in DIAGNOSTIC POSITION.
0>Diag level set to MIN.
0>MFG scrpt mode set NORM
0>I/O port set to serial TTYA.
0>
0>Start selftest...
0>Init CPU
0> Cheetah_plus Version 2.3
0>DMMU Registers Access
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Probe Ecache
0> Size = 00000000.00800000...
0>Ecache Data Bitwalk
0>Ecache Address Bitwalk
0>Scrub and Setup Ecache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test and Init Temp Mailbox
2>Init CPU
2> Cheetah_plus Version 2.3
2>DMMU Registers Access
2>DMMU TLB DATA RAM Access
2>DMMU TLB TAGS Access
2>IMMU Registers Access
2>IMMU TLB DATA RAM Access
2>IMMU TLB TAGS Access
2>Probe Ecache
2> Size = 00000000.00800000...
2>Ecache Data Bitwalk
2>Ecache Address Bitwalk
2>Scrub and Setup Ecache
2>Setup and Enable DMMU
2>Setup DMMU Miss Handler
2>Test and Init Temp Mailbox
0>Initializing Scan Database
0>Mask DAR errors off
0>Init MDR DTL
0>Init DAR DTL
0>Enable Partial DAR error
0>Init DCS DTL
0>Init I2C
0>Unquiesce Safari
0>Margin all voltages to nominal
0>Scan ring integrity
0>INFO: H/W under test = CPU Board Slot B (Cheetah 1, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot B (Cheetah 3, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>INFO: H/W under test = CPU Board Slot C (Cheetah 4, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 5, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot C (Cheetah 6, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 7, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>Set Trip Temp CPU 0 to 110C
0>Set Trip Temp CPU 2 to 110C
0>WED FEB27 8:19:34 GMT 13
0>Safari quick check
0> to IO-bridge_0
0> to IO-bridge_1
0>Safari fullcheck
0> to IO-bridge_0
0> to IO-bridge_1
0>Disable Cheetah 0 error checking
0>Disable Cheetah 2 error checking
0>Probe and Setup Memory
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0>
0>Data Bitwalk on Master
0> Test Bank 0.
0> Test Bank 1.
0> Test Bank 2.
0> Test Bank 3.
0>Address Bitwalk on Master
0>INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 3: 00000003.00000000 to 00000003.200000
00.
0>Set Mailbox
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 46d6.
0>The Memory's Content Size value is 93cd2.
0>Success...Checksum on Memory Validated.
0>Safari quick check
0> to IO-bridge_0
0> to IO-bridge_1
0>Safari fullcheck
0> to IO-bridge_0
0> to IO-bridge_1
2>Safari quick check
2> to IO-bridge_0
2> to IO-bridge_1
2>Safari fullcheck
2> to IO-bridge_0
2> to IO-bridge_1
2>Probe and Setup Memory
2>INFO: 512MB Bank 0
2>INFO: 512MB Bank 1
2>INFO: 512MB Bank 2
2>INFO: 512MB Bank 3
2>
2>Set Mailbox
0>Data Bitwalk on Slave 2
0> Test Bank 0.
0> Test Bank 1.
0> Test Bank 2.
0> Test Bank 3.
0>Address Bitwalk on Slave 2
0>INFO: Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 1: 00000021.00000000 to 00000021.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 3: 00000023.00000000 to 00000023.200000
00.
2>Setup Final DMMU Entries
2>Map Slave POST to master memory
2>Print Mem Config
2>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2>Memory in non-interleave config:
2> Bank 0 512MB : 00000020.00000000 -> 00000020.20000000.
2> Bank 1 512MB : 00000021.00000000 -> 00000021.20000000.
2> Bank 2 512MB : 00000022.00000000 -> 00000022.20000000.
2> Bank 3 512MB : 00000023.00000000 -> 00000023.20000000.
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0>Memory in non-interleave config:
0> Bank 0 512MB : 00000000.00000000 -> 00000000.20000000.
0> Bank 1 512MB : 00000001.00000000 -> 00000001.20000000.
0> Bank 2 512MB : 00000002.00000000 -> 00000002.20000000.
0> Bank 3 512MB : 00000003.00000000 -> 00000003.20000000.
2>Scrub Memory
0>Scrub Memory
2>Quick Block Mem Test
0>Quick Block Mem Test
2>Quick Test 16777216 bytes at 00000020.00000000
0>Quick Test 16777216 bytes at 00000000.00600000
2>WARNING: TEST = Quick Block Mem Test
2>H/W under test = CPU2, All CPU2 Memory
2>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000071
Trap PC ffffffff.f0137d6c
Trap Level 00000000.00000001
AFSR 00000000.00000000
AFAR 00000000.00000000
2>END_WARNING
2> No Errors in afsr reg
2>ERROR: TEST = Quick Block Mem Test
2>H/W under test = CPU2, All CPU2 Memory
2>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2>MSG =
*** Test Failed!! ***
2>END_ERROR
0>40% Done...
2>Flush Caches
0>Flush Caches
自检停在这
做个最大化检测 本帖最后由 linton 于 2013-02-27 17:10 编辑
回复 2# 119beyond
自检信息：
<*>
Hardware Power On
@(#)OBP4.7.5 2003/01/08 11:36 Sun Fire 880
Front Panel Keyswitch is in Diagnostic position.
Online: CPU0 CPU2*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing MDR via JTAG...Done
Enabling DAR error circuitry...Done
Probing Motherboard....part# 501-6323-02 serial# 017270
Safari min 100MHz, cumulative 100MHz;max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Board......part# 501-5142-18 serial# 043616
Probing System RSC.....part# 501-5856-06 serial# 161689
Probing PwrDistBoard...part# 375-0071-03 serial# N36370
Probing PowerSupply0...part# 300-1353-02 serial# M12988
Probing PowerSupply1...part# 300-1353-02 serial# M12991
Probing PowerSupply2...part# 300-1353-02 serial# M12986
Probing GPTwo Slot A...part# 501-6334-03 serial# 097940
Safari min 100MHz, cumulative 100MHz;max 150MHz, cumulative 150MHz
CPU rated speed 900MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...No module detected
Probing GPTwo Slot C...No module detected
Probing GPTwo Slot D...No module detected
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU0 Rated Speed 900MHz, Safari 150MHz, want 6:1, got 6:1 ==> CPU 900MHz
Ecache 8MB 3.3ns mode=3-3-3 2-way ECCR: 0000.0000.0309.4400
... CPU2 Rated Speed 900MHz, Safari 150MHz, want 6:1, got 6:1 ==> CPU 900MHz
Ecache 8MB 3.3ns mode=3-3-3 2-way ECCR: 0000.0000.0309.4400 ...Done
Setting system speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP4.7.5 2003/01/08 11:36 Sun Fire 880
Front Panel Keyswitch is in Diagnostic position.
Online:CPU0 Ultra-III+ (v2.3) 6:1 900MHz 8MB 3:1 ECache
Online: *CPU2 Ultra-III+ (v2.3) 6:1 900MHz 8MB 3:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.2042
0>@(#) Daktari POST 4.7.4 2002/12/23 15:45
/dat/fw/work/staff/firmware_re/post/post-build-4.7.4/Camelot/daktari/inte
grated(firmware_re)
0>Jump from OBP->POST.
0>CPUs present in system: 0 2
0>Keyswitch in DIAGNOSTIC POSITION.
0>Diag level set to MIN.
0>MFG scrpt mode set NORM
0>I/O port set to serial TTYA.
0>
0>Start selftest...
0>Init CPU
0> Cheetah_plus Version 2.3
0>DMMU Registers Access
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Probe Ecache
0> Size = 00000000.00800000...
0>Ecache Data Bitwalk
0>Ecache Address Bitwalk
0>Scrub and Setup Ecache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test and Init Temp Mailbox
2>Init CPU
2> Cheetah_plus Version 2.3
2>DMMU Registers Access
2>DMMU TLB DATA RAM Access
2>DMMU TLB TAGS Access
2>IMMU Registers Access
2>IMMU TLB DATA RAM Access
2>IMMU TLB TAGS Access
2>Probe Ecache
2> Size = 00000000.00800000...
2>Ecache Data Bitwalk
2>Ecache Address Bitwalk
2>Scrub and Setup Ecache
2>Setup and Enable DMMU
2>Setup DMMU Miss Handler
2>Test and Init Temp Mailbox
0>Initializing Scan Database
0>Mask DAR errors off
0>Init MDR DTL
0>Init DAR DTL
0>Enable Partial DAR error
0>Init DCS DTL
0>Init I2C
0>Unquiesce Safari
0>Margin all voltages to nominal
0>Scan ring integrity
0>INFO: H/W under test = CPU Board Slot B (Cheetah 1, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot B (Cheetah 3, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>INFO: H/W under test = CPU Board Slot C (Cheetah 4, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 5, DCDS , SRAMs) Scan Ri
ng NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot C (Cheetah 6, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 7, SRAMs) Scan Ring NOT Prese
nt or Shut OFF
0>Set Trip Temp CPU 0 to 110C
0>Set Trip Temp CPU 2 to 110C
0>WED FEB27 8:19:34 GMT 13
0>Safari quick check
0> to IO-bridge_0
0> to IO-bridge_1
0>Safari fullcheck
0> to IO-bridge_0
0> to IO-bridge_1
0>Disable Cheetah 0 error checking
0>Disable Cheetah 2 error checking
0>Probe and Setup Memory
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0>
0>Data Bitwalk on Master
0> Test Bank 0.
0> Test Bank 1.
0> Test Bank 2.
0> Test Bank 3.
0>Address Bitwalk on Master
0>INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.200000
00.
0>INFO: Addr walk mem test on CPU 0 Bank 3: 00000003.00000000 to 00000003.200000
00.
0>Set Mailbox
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 46d6.
0>The Memory's Content Size value is 93cd2.
0>Success...Checksum on Memory Validated.
0>Safari quick check
0> to IO-bridge_0
0> to IO-bridge_1
0>Safari fullcheck
0> to IO-bridge_0
0> to IO-bridge_1
2>Safari quick check
2> to IO-bridge_0
2> to IO-bridge_1
2>Safari fullcheck
2> to IO-bridge_0
2> to IO-bridge_1
2>Probe and Setup Memory
2>INFO: 512MB Bank 0
2>INFO: 512MB Bank 1
2>INFO: 512MB Bank 2
2>INFO: 512MB Bank 3
2>
2>Set Mailbox
0>Data Bitwalk on Slave 2
0> Test Bank 0.
0> Test Bank 1.
0> Test Bank 2.
0> Test Bank 3.
0>Address Bitwalk on Slave 2
0>INFO: Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 1: 00000021.00000000 to 00000021.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.200000
00.
0>INFO: Addr walk mem test on CPU 2 Bank 3: 00000023.00000000 to 00000023.200000
00.
2>Setup Final DMMU Entries
2>Map Slave POST to master memory
2>Print Mem Config
2>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2>Memory in non-interleave config:
2> Bank 0 512MB : 00000020.00000000 -> 00000020.20000000.
2> Bank 1 512MB : 00000021.00000000 -> 00000021.20000000.
2> Bank 2 512MB : 00000022.00000000 -> 00000022.20000000.
2> Bank 3 512MB : 00000023.00000000 -> 00000023.20000000.
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0>Memory in non-interleave config:
0> Bank 0 512MB : 00000000.00000000 -> 00000000.20000000.
0> Bank 1 512MB : 00000001.00000000 -> 00000001.20000000.
0> Bank 2 512MB : 00000002.00000000 -> 00000002.20000000.
0> Bank 3 512MB : 00000003.00000000 -> 00000003.20000000.
2>Scrub Memory
0>Scrub Memory
2>Quick Block Mem Test
0>Quick Block Mem Test
2>Quick Test 16777216 bytes at 00000020.00000000
0>Quick Test 16777216 bytes at 00000000.00600000
2>WARNING: TEST = Quick Block Mem Test
2>H/W under test = CPU2, All CPU2 Memory
2>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000071
Trap PC ffffffff.f0137d6c
Trap Level 00000000.00000001
AFSR 00000000.00000000
AFAR 00000000.00000000
2>END_WARNING
2> No Errors in afsr reg
2>ERROR: TEST = Quick Block Mem Test
2>H/W under test = CPU2, All CPU2 Memory
2>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2>MSG =
*** Test Failed!! ***
2>END_ERROR
0>40% Done...
2>Flush Caches
0>Flush Caches
自检停在这
用串口连接上去，做最大化自检，他会显示出来是那个部件坏了。
话说这个串口线不好找。
坚着的25针 217.2>H/W under test = CPU2, All CPU2 Memory
218.2>Repair Instructions: Replace items in order listed by 'H/W under test' above.
POST信息很清楚了～ 东方蜘蛛 发表于 2013-02-27 17:45 static/image/common/back.gif
217.2>H/W under test = CPU2, All CPU2 Memory
218.2>Repair Instructions: Replace items in order li ...
把 CPU2, All CPU2 Memory 全部去掉，是否可以呢？ 提示ALL CPU2 Memory内存都坏掉的可能性就很小了，应该是CPU板有问题了，建议CPU板和内存都做好换的准备。 本帖最后由 东方蜘蛛 于 2013-03-01 09:59 编辑
linton 发表于 2013-02-28 11:18 static/image/common/back.gif
把 CPU2, All CPU2 Memory 全部去掉，是否可以呢？
把CPU2所在的SLOT A板子重新插拔几次看看，或者换槽位试试，问题终究是要解决嘛～ 串口买个头子自己做一个就行了。。
自检信息也写的很清楚。
另外蜘蛛也说的很清楚了。。可以so easy的解决掉了。
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