V440无法开机，日志如下，求分析。
--------------------------------------------------------最大化自检开机-----------------------------------------------------------ALOM BOOTMON v1.6.9
ALOM Build Release: 001
Reset register: e0000000 EHRS ESRS LLRS
ALOM POST 1.0
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Test for shorted address lines
Memory Address Lines Test, PASSED.
Memory Parity Test
Memory Parity Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitor for Handshake
ALOM POST 1.0
Status = 00007fff
Returned from Boot Monitor and Handshake
Clearing Memory Cells
Memory Clean Complete
Loading the runtime image...
SC Alert: SC System booted.
Sun(tm) Advanced Lights Out Manager 1.6.9 (gg-sb2)
Full VxDiag Tests
BASIC TOD TEST
Read the TOD Clock: WED AUG 13 14:42:50 2014
Wait, 1 - 3 seconds
Read the TOD Clock: WED AUG 13 14:42:52 2014
BASIC TOD TEST, PASSED
ETHERNET CPU LOOPBACK TEST
50 BYTE PACKET - a 0 in field of 1's.
50 BYTE PACKET - a 1 in field of 0's.
900 BYTE PACKET- pseudo-random data.
ETHERNET CPU LOOPBACK TEST, PASSED
Full VxDiag Tests - PASSED
Status summary-Status = 7FFF
VxDiag - -PASSED
POST - -PASSED
LOOPBACK- -PASSED
I2C - -PASSED
EPROM - -PASSED
FRU PROM- -PASSED
ETHERNET- -PASSED
MAIN CRC- -PASSED
BOOT CRC- -PASSED
TTYD - -PASSED
TTYC - -PASSED
MEMORY - -PASSED
MPC850 - -PASSED
Please login:
SC Alert: Host System has Reset
Serial line login timeout, returns to console stream.
Enter #. to return to ALOM.
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>TestMailbox
0>Scrub Mailbox
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
0>Set Timing
0> UltraSPARC IIIi, Version 3.4
0>
0>ERROR: TEST = Check cpu synch var CPU 1
0>H/W under test = CPU1 Basic, Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = CPU 1 failed IO-Bridge 1 SRAM access, offline cpu.
0>END_ERROR
0>
0>ERROR: TEST = Check cpu synch var CPU 1
0>H/W under test = CPU1 Basic, Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG =
*** Test Failed!! ***
0>END_ERROR
2>Init CPU
3>Init CPU
2> UltraSPARC IIIi, Version 3.4
3> UltraSPARC IIIi, Version 3.4
2>DMMU
3>DMMU
2>DMMU TLB DATA RAM Access
3>DMMU TLB DATA RAM Access
2>DMMU TLB TAGS Access
3>DMMU TLB TAGS Access
2>IMMU Registers Access
3>IMMU Registers Access
2>IMMU TLB DATA RAM Access
3>IMMU TLB DATA RAM Access
2>IMMU TLB TAGS Access
3>IMMU TLB TAGS Access
2>Init mmu regs
3>Init mmu regs
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2> Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3> Size = 00000000.00100000...
2>L2 Cache Tags Test
3>L2 Cache Tags Test
2>Scrub and Setup L2 Cache
3>Scrub and Setup L2 Cache
2>Setup and Enable DMMU
3>Setup and Enable DMMU
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
2>TestMailbox
3>TestMailbox
2>Scrub Mailbox
3>Scrub Mailbox
2>CPU Tick and Tick Compare Registers Test
3>CPU Tick and Tick Compare Registers Test
2>CPU Stick and Stick Compare Registers Test
3>CPU Stick and Stick Compare Registers Test
2>Setup Int Handlers
3>Setup Int Handlers
0>Interrupt Crosscall.....
0>Setup Int Handlers
0>Send Int CPU 2
0>Send Int CPU 3
2>Send Int to Master CPU
3>Send Int to Master CPU
0>MB: Part-Dash-Rev#:5016344-10-50Serial#:058750
0>CPU0: Part-Dash-Rev#:5017029-02-51Serial#:019718
0>CPU2: Part-Dash-Rev#:5017029-02-51Serial#:019697
0>CPU3: Part-Dash-Rev#:5017029-02-51Serial#:019705
0>CPU0 DIMM B0/D0 J0601:
0>Part#:72D64500GR7B Serial#:0706cd20Date Code:0450Rev#:022f
0>CPU0 DIMM B0/D1 J0602:
0>Part#:72D64500GR7B Serial#:0706cd25Date Code:0450Rev#:022f
0>CPU0 DIMM B1/D0 J0701:
0>Part#:72D64500GR7B Serial#:0706cf24Date Code:0450Rev#:022f
0>CPU0 DIMM B1/D1 J0702:
0>Part#:72D64500GR7B Serial#:0706ca22Date Code:0450Rev#:022f
0>CPU2 DIMM B0/D0 J0601:
0>Part#:72D64500GR7B Serial#:0105c115Date Code:0452Rev#:0210
0>CPU2 DIMM B0/D1 J0602:
0>Part#:72D64500GR7B Serial#:0105be13Date Code:0452Rev#:0210
0>CPU2 DIMM B1/D0 J0701:
0>Part#:72D64500GR7B Serial#:0105bf14Date Code:0452Rev#:0210
0>CPU2 DIMM B1/D1 J0702:
0>Part#:72D64500GR7B Serial#:0105bd13Date Code:0452Rev#:0210
0>CPU3 DIMM B0/D0 J0601:
0>Part#:72D64500GR7B Serial#:0105bc15Date Code:0452Rev#:0210
0>CPU3 DIMM B0/D1 J0602:
0>Part#:72D64500GR7B Serial#:0105bc16Date Code:0452Rev#:0210
0>CPU3 DIMM B1/D0 J0701:
0>Part#:72D64500GR7B Serial#:0105bd14Date Code:0452Rev#:0210
0>CPU3 DIMM B1/D1 J0702:
0>Part#:72D64500GR7B Serial#:0105c317Date Code:0452Rev#:0210
0>Set CPU/System Speed
0>......
0>Send MC Timing CPU 2
0>Send MC Timing CPU 3
0>Init Memory.....
0>Probe Dimms
2>Probe Dimms
3>Probe Dimms
2>Init Mem Controller Regs
3>Init Mem Controller Regs
0>Init Mem Controller Regs
2>Set JBUS config reg
3>Set JBUS config reg
0>Set JBUS config reg
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Do PLL reset
0>Setting timing to 7:1 10:1, system frequency 183 MHz, CPU frequency 1281 MHz
SC Alert: Host System has Reset
然后就再没有输出了。
--------------------------------------------------------关机，非最大化自检开机----------------------------------------------------
SC Alert: Host system has shut down.
SC Alert: Host System has Reset
NOTICE: Not running POST because diag-level = off.
Configuring system memory & CPU(s)
Probing system devices
然后就再没有输出了。 0>ERROR: TEST = Check cpu synch var CPU 1
0>H/W under test = CPU1 Basic, Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above. CPU 1挂了，拔掉吧 :cry: 支持一下，运气不好，偶的一台440也亮故障灯，过几个小时就自动关机了
偶也自检看看 有一台闲置的完好v440，有人要没有，2个cpu 4g内存。
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