With an 8-stage pipeline and a maximum clock frequency exceeding 1400 MHz in 40nm, the 24K family of cores enable SoC designers to reduce product costs and speed time-to-market by giving them the performance headroom to implement more features now and upgrades in the future with software flexibility rather than rigid, fixed hardware.
Cadence, Synopsys, Magma and other EDA industry leaders help minimize design time and offer a proven path to silicon by co-developing tailored SoC design methodologies. This couples the high-performance, low-power 24K cores with cutting-edge core hardening technologies.
By standardizing the core interface on OCP (www.ocpip.org), the 24K cores accelerate time-to-market by enabling easy reuse of standard SoC IP. Memory controllers, bus interconnects and other standardized peripherals are now easily integrated through common on-chip interfaces.
The highly-scalable 24K microarchitecture implements the industry-standard MIPS32 Release 2 architecture, which includes features such as enhanced bit-field manipulation, reduced interrupt latency and enhanced cache control.
A rich environment of third-party tools and software support the 24K family of cores.3
1MIPS32® 74K®
A 15-stage asymmetric dual-issue pipeline, out-of-order instruction dispatch/completion and fully synthesizable design gives SoC developers full flexibility to port the design across different processes and accelerate time-to-market
Two versions of the 74K family are available - 74Kc™ (standard) and 74Kf™ (high-performance Floating Point Unit)
Standard OCP bus interface provides backward-compatibility with existing 24K, 24KE and 34K cores
A rich ecosystem of third-party software and debug tools coupled with software and tools support from MIPS Technologies
Back-end EDA flow support for Cadence, Magma and Synopsys design tools