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标题:
mips参数传递及堆栈分配实验
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作者:
nizqsut
时间:
2011-12-21 08:41
标题:
mips参数传递及堆栈分配实验
/*
* by nizqsut@163.com
**/
/*
* 思考：
* arg_in_x()函数都是直接return，
* 为什么还要不参数保存到堆栈里面？
* */
int arg_in_4(int a, int b, int c, int d)
{
return 4;
}
/* 前4个参数使用a0 ~ a3传，第5个到第8个使用t0 ~ t3传 */
int arg_in_5(int a, int b, int c, int d, int e)
{
return 5;
}
int arg_in_6(int a, int b, int c, int d, int e, int f)
{
return 6;
}
int arg_in_7(int a, int b, int c, int d, int e, int f, int g)
{
return 7;
}
int arg_in_8(int a, int b, int c, int d,
int e, int f, int g, int h)
{
return 8;
}
/* 参数超过8个后，从第9个开始好像没有将参数压栈了 */
int arg_in_9(int a, int b, int c, int d,
int e, int f, int g, int h, int i)
{
return 9;
}
int arg_in_10(int a, int b, int c, int d,
int e, int f, int g, int h,
int i, int j)
{
return 10;
}
int stact_view(void)
{
char c0, c1, c2;
long l0, l1, l2;
int ar0[10], ar1[10];
int i0, i1, i2;
char ar_c[40];
c0 = 10;
c1 = 11;
c2 = 12;
i0 = 20;
i1 = 21;
i2 = 22;
l0 = 30;
l1 = 31;
l2 = 32;
ar0[0] = 55;
ar0[9] = 44;
ar1[0] = 88;
ar1[9] = 77;
ar_c[0] = 0xaa;
ar_c[39] = 0xbb;
return 1;
}
int test_arg(void)
{
arg_in_4(0x10, 0x20, 0x30, 0x40);
return 0;
}
------------------------------------------------------------------
mips_arg.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <arg_in_4>:
0: 67bdffe8 daddiu sp,sp,-24
4: ffbe0010 sd s8,16(sp)
8: 03a0f02d move s8,sp
c: 0080102d move v0,a0
10: 00a0182d move v1,a1
14: 00c0202d move a0,a2
18: 00e0282d move a1,a3
1c: 00021000 sll v0,v0,0x0
20: afc20000 sw v0,0(s8)
24: 00031000 sll v0,v1,0x0
28: afc20004 sw v0,4(s8)
2c: 00041000 sll v0,a0,0x0
30: afc20008 sw v0,8(s8)
34: 00051000 sll v0,a1,0x0
38: afc2000c sw v0,12(s8)
3c: 24020004 li v0,4
40: 03c0e82d move sp,s8
44: dfbe0010 ld s8,16(sp)
48: 67bd0018 daddiu sp,sp,24
4c: 03e00008 jr ra
50: 00000000 nop
00000054 <arg_in_5>:
54: 67bdffe0 daddiu sp,sp,-32
58: ffbe0018 sd s8,24(sp)
5c: 03a0f02d move s8,sp
60: 0080102d move v0,a0
64: 00a0182d move v1,a1
68: 00c0202d move a0,a2
6c: 00e0282d move a1,a3
70: 0100302d move a2,t0
74: 00021000 sll v0,v0,0x0
78: afc20000 sw v0,0(s8)
7c: 00031000 sll v0,v1,0x0
80: afc20004 sw v0,4(s8)
84: 00041000 sll v0,a0,0x0
88: afc20008 sw v0,8(s8)
8c: 00051000 sll v0,a1,0x0
90: afc2000c sw v0,12(s8)
94: 00061000 sll v0,a2,0x0
98: afc20010 sw v0,16(s8)
9c: 24020005 li v0,5
a0: 03c0e82d move sp,s8
a4: dfbe0018 ld s8,24(sp)
a8: 67bd0020 daddiu sp,sp,32
ac: 03e00008 jr ra
b0: 00000000 nop
000000b4 <arg_in_6>:
b4: 67bdffe0 daddiu sp,sp,-32
b8: ffbe0018 sd s8,24(sp)
bc: 03a0f02d move s8,sp
c0: 0080102d move v0,a0
c4: 00a0182d move v1,a1
c8: 00c0202d move a0,a2
cc: 00e0282d move a1,a3
d0: 0100302d move a2,t0
d4: 0120382d move a3,t1
d8: 00021000 sll v0,v0,0x0
dc: afc20000 sw v0,0(s8)
e0: 00031000 sll v0,v1,0x0
e4: afc20004 sw v0,4(s8)
e8: 00041000 sll v0,a0,0x0
ec: afc20008 sw v0,8(s8)
f0: 00051000 sll v0,a1,0x0
f4: afc2000c sw v0,12(s8)
f8: 00061000 sll v0,a2,0x0
fc: afc20010 sw v0,16(s8)
100: 00071000 sll v0,a3,0x0
104: afc20014 sw v0,20(s8)
108: 24020006 li v0,6
10c: 03c0e82d move sp,s8
110: dfbe0018 ld s8,24(sp)
114: 67bd0020 daddiu sp,sp,32
118: 03e00008 jr ra
11c: 00000000 nop
00000120 <arg_in_7>:
120: 67bdffd8 daddiu sp,sp,-40
124: ffbe0020 sd s8,32(sp)
128: 03a0f02d move s8,sp
12c: 0080102d move v0,a0
130: 00a0182d move v1,a1
134: 00c0202d move a0,a2
138: 00e0282d move a1,a3
13c: 0100302d move a2,t0
140: 0120382d move a3,t1
144: 0140402d move t0,t2
148: 00021000 sll v0,v0,0x0
14c: afc20000 sw v0,0(s8)
150: 00031000 sll v0,v1,0x0
154: afc20004 sw v0,4(s8)
158: 00041000 sll v0,a0,0x0
15c: afc20008 sw v0,8(s8)
160: 00051000 sll v0,a1,0x0
164: afc2000c sw v0,12(s8)
168: 00061000 sll v0,a2,0x0
16c: afc20010 sw v0,16(s8)
170: 00071000 sll v0,a3,0x0
174: afc20014 sw v0,20(s8)
178: 00081000 sll v0,t0,0x0
17c: afc20018 sw v0,24(s8)
180: 24020007 li v0,7
184: 03c0e82d move sp,s8
188: dfbe0020 ld s8,32(sp)
18c: 67bd0028 daddiu sp,sp,40
190: 03e00008 jr ra
194: 00000000 nop
00000198 <arg_in_8>:
198: 67bdffd8 daddiu sp,sp,-40
19c: ffbe0020 sd s8,32(sp)
1a0: 03a0f02d move s8,sp
1a4: 0080102d move v0,a0
1a8: 00a0182d move v1,a1
1ac: 00c0202d move a0,a2
1b0: 00e0282d move a1,a3
1b4: 0100302d move a2,t0
1b8: 0120382d move a3,t1
1bc: 0140402d move t0,t2
1c0: 0160482d move t1,t3
1c4: 00021000 sll v0,v0,0x0
1c8: afc20000 sw v0,0(s8)
1cc: 00031000 sll v0,v1,0x0
1d0: afc20004 sw v0,4(s8)
1d4: 00041000 sll v0,a0,0x0
1d8: afc20008 sw v0,8(s8)
1dc: 00051000 sll v0,a1,0x0
1e0: afc2000c sw v0,12(s8)
1e4: 00061000 sll v0,a2,0x0
1e8: afc20010 sw v0,16(s8)
1ec: 00071000 sll v0,a3,0x0
1f0: afc20014 sw v0,20(s8)
1f4: 00081000 sll v0,t0,0x0
1f8: afc20018 sw v0,24(s8)
1fc: 00091000 sll v0,t1,0x0
200: afc2001c sw v0,28(s8)
204: 24020008 li v0,8
208: 03c0e82d move sp,s8
20c: dfbe0020 ld s8,32(sp)
210: 67bd0028 daddiu sp,sp,40
214: 03e00008 jr ra
218: 00000000 nop
0000021c <arg_in_9>:
21c: 67bdffd8 daddiu sp,sp,-40
220: ffbe0020 sd s8,32(sp)
224: 03a0f02d move s8,sp
228: 0080102d move v0,a0
22c: 00a0182d move v1,a1
230: 00c0202d move a0,a2
234: 00e0282d move a1,a3
238: 0100302d move a2,t0
23c: 0120382d move a3,t1
240: 0140402d move t0,t2
244: 0160482d move t1,t3
248: 00021000 sll v0,v0,0x0
24c: afc20000 sw v0,0(s8)
250: 00031000 sll v0,v1,0x0
254: afc20004 sw v0,4(s8)
258: 00041000 sll v0,a0,0x0
25c: afc20008 sw v0,8(s8)
260: 00051000 sll v0,a1,0x0
264: afc2000c sw v0,12(s8)
268: 00061000 sll v0,a2,0x0
26c: afc20010 sw v0,16(s8)
270: 00071000 sll v0,a3,0x0
274: afc20014 sw v0,20(s8)
278: 00081000 sll v0,t0,0x0
27c: afc20018 sw v0,24(s8)
280: 00091000 sll v0,t1,0x0
284: afc2001c sw v0,28(s8)
288: 24020009 li v0,9
28c: 03c0e82d move sp,s8
290: dfbe0020 ld s8,32(sp)
294: 67bd0028 daddiu sp,sp,40
298: 03e00008 jr ra
29c: 00000000 nop
000002a0 <arg_in_10>:
2a0: 67bdffd8 daddiu sp,sp,-40
2a4: ffbe0020 sd s8,32(sp)
2a8: 03a0f02d move s8,sp
2ac: 0080102d move v0,a0
2b0: 00a0182d move v1,a1
2b4: 00c0202d move a0,a2
2b8: 00e0282d move a1,a3
2bc: 0100302d move a2,t0
2c0: 0120382d move a3,t1
2c4: 0140402d move t0,t2
2c8: 0160482d move t1,t3
2cc: 00021000 sll v0,v0,0x0
2d0: afc20000 sw v0,0(s8)
2d4: 00031000 sll v0,v1,0x0
2d8: afc20004 sw v0,4(s8)
2dc: 00041000 sll v0,a0,0x0
2e0: afc20008 sw v0,8(s8)
2e4: 00051000 sll v0,a1,0x0
2e8: afc2000c sw v0,12(s8)
2ec: 00061000 sll v0,a2,0x0
2f0: afc20010 sw v0,16(s8)
2f4: 00071000 sll v0,a3,0x0
2f8: afc20014 sw v0,20(s8)
2fc: 00081000 sll v0,t0,0x0
300: afc20018 sw v0,24(s8)
304: 00091000 sll v0,t1,0x0
308: afc2001c sw v0,28(s8)
30c: 2402000a li v0,10
310: 03c0e82d move sp,s8
314: dfbe0020 ld s8,32(sp)
318: 67bd0028 daddiu sp,sp,40
31c: 03e00008 jr ra
320: 00000000 nop
00000324 <stact_view>:
324: 67bdff50 daddiu sp,sp,-176
328: ffbe00a8 sd s8,168(sp)
32c: 03a0f02d move s8,sp
330: 2402000a li v0,10
334: a3c2002a sb v0,42(s8)
338: 2402000b li v0,11
33c: a3c20029 sb v0,41(s8)
340: 2402000c li v0,12
344: a3c20028 sb v0,40(s8)
348: 24020014 li v0,20
34c: afc20008 sw v0,8(s8)
350: 24020015 li v0,21
354: afc20004 sw v0,4(s8)
358: 24020016 li v0,22
35c: afc20000 sw v0,0(s8)
360: 2402001e li v0,30
364: ffc20020 sd v0,32(s8)
368: 2402001f li v0,31
36c: ffc20018 sd v0,24(s8)
370: 24020020 li v0,32
374: ffc20010 sd v0,16(s8)
378: 24020037 li v0,55
37c: afc20030 sw v0,48(s8)
380: 2402002c li v0,44
384: afc20054 sw v0,84(s8)
388: 24020058 li v0,88
38c: afc20058 sw v0,88(s8)
390: 2402004d li v0,77
394: afc2007c sw v0,124(s8)
398: 2402ffaa li v0,-86
39c: a3c20080 sb v0,128(s8)
3a0: 2402ffbb li v0,-69
3a4: a3c200a7 sb v0,167(s8)
3a8: 24020001 li v0,1
3ac: 03c0e82d move sp,s8
3b0: dfbe00a8 ld s8,168(sp)
3b4: 67bd00b0 daddiu sp,sp,176
3b8: 03e00008 jr ra
3bc: 00000000 nop
000003c0 <test_arg>:
3c0: 67bdfff0 daddiu sp,sp,-16
3c4: ffbf0008 sd ra,8(sp)
3c8: ffbe0000 sd s8,0(sp)
3cc: 03a0f02d move s8,sp
3d0: 24040010 li a0,16
3d4: 24050020 li a1,32
3d8: 24060030 li a2,48
3dc: 24070040 li a3,64
3e0: 0c000000 jal 0 <arg_in_4>
3e4: 00000000 nop
3e8: 0000102d move v0,zero
3ec: 03c0e82d move sp,s8
3f0: dfbf0008 ld ra,8(sp)
3f4: dfbe0000 ld s8,0(sp)
3f8: 67bd0010 daddiu sp,sp,16
3fc: 03e00008 jr ra
400: 00000000 nop
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