Whenever there is a write to a linear address, the processor sets the dirty flag (if it is
not already set) in the paging-structure entry that identifies the final physical
address for the linear address (either a PTE or a paging-structure entry in which the
PS flag is 1).
...These flags are “sticky,” meaning that,
once set, the processor does not clear them; only software can clear them.
“paging-structure entry that identifies the final physical
address for the linear address (either a PTE or a paging-structure entry in which the
PS flag is 1).”
这里说的paging-structure entry应该是指pte吧?跟内核管理的page结构没啥关系吧? 作者: chenyu105 时间: 2014-06-19 11:05 回复 20# humjb_1983
以下是ARM的註解
/*
* Hardware-wise, we have a two level page table structure, where the first
* level has 4096 entries, and the second level has 256 entries. Each entry
* is one 32-bit word. Most of the bits in the second level entry are used
* by hardware, and there aren't any "accessed" and "dirty" bits.