@(#) Sun Ultra 450 3.18 Version 0 created 2000/05/26 05:51
Offline: CPU0 (MD'ed)
Online: CPU1 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Online: CPU2 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Online: CPU3 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Probing keyboard for L1/L1-D...Done
Executing Power On SelfTest w/%o0 = 0000.0000.0010.1001
1>;
1>;
1>;INFO: Processor 1 is master CPU.
1>;INFO: Motherboard rev FCS
1>;
1>; <00>; Init System BSS
1>; <00>; NVRAM Battery Detect Test
1>; <00>; NVRAM Scratch Addr Test
1>; <00>; DMMU TLB Tag Access Test
1>; <00>; DMMU TLB RAM Access Test
1>; <00>; Probe Ecache
1>;INFO: 4096KB Ecache
1>; <00>; Ecache RAM Addr Test
1>; <00>; Ecache Tag Addr Test
1>; <00>; Invalidate Ecache Tags
1>; <00>; SC Dtag Probe
1>;INFO: Dtag supports up to 8MB Ecache
1>;INFO: Processor 0 is missing or disabled.
1>;INFO: Processor 2 - UltraSPARC-II.
1>;INFO: Processor 3 - UltraSPARC-II.
1>; <00>; Init SC Regs
1>; <00>; SC Address Reg Test
1>; <00>; SC Reg Index Test
1>; <00>; SC Regs Test
1>; <00>; SC Dtag RAM Addr Test
1>; <00>; SC Dtag RAM Addr Test
1>; <00>; SC Dtag Init
1>; <00>; Init SC Regs
1>; <00>; SC Cache Size Init
3>; <00>; Probe Ecache
2>; <00>; Probe Ecache
3>;INFO: 4096KB Ecache
2>;INFO: 4096KB Ecache
3>; <00>; Ecache RAM Addr Test
2>; <00>; Ecache RAM Addr Test
3>; <00>; Ecache Tag Addr Test
2>; <00>; Ecache Tag Addr Test
3>; <00>; Invalidate Ecache Tags
2>; <00>; Invalidate Ecache Tags
1>; <00>; Synch up Processor Ecache Sizes
3>; <00>; Synch up Processor Ecache Sizes
2>; <00>; Synch up Processor Ecache Sizes
1>; <00>; Probe Memory
1>;INFO: 1024MB Bank 0
1>;INFO: 1024MB Bank 1
1>;INFO: No memory detected in Bank 2
1>;INFO: No memory detected in Bank 3
1>; <00>; Test Memory Data Lines
1>; <00>; Test Memory Address Lines
1>; <00>; Malloc Post Memory
1>; <00>; Init Post Memory
1>; <00>; Map PROM/STACK/NVRAM in DMMU
1>; <00>; Memory Stack Test
1>; <00>; Init Memory
1>; <00>; ECC Memory Addr Test
3>; <00>; DMMU TLB Tag Access Test
2>; <00>; DMMU TLB Tag Access Test
3>; <00>; DMMU TLB RAM Access Test
2>; <00>; DMMU TLB RAM Access Test
3>; <00>; Map PROM/STACK/NVRAM in DMMU
2>; <00>; Map PROM/STACK/NVRAM in DMMU
3>; <00>; Update Slave Stack/Frame Ptrs
2>; <00>; Update Slave Stack/Frame Ptrs
2>; <00>; Memory Data Lines
2>; <00>; Memory Address Lines
3>; <00>; Memory Data Lines
3>; <00>; Memory Address Lines
1>; <00>; V9 Instruction Test
3>; <00>; V9 Instruction Test
2>; <00>; V9 Instruction Test
1>; <00>; Memory Addr w/ Ecache Test
1>; <00>; Block Memory Addr Test
1>; <00>; Copy Post to Memory
1>; <00>; Map/Exec POST from Memory
1>; <00>; Map alternate CPUs
1>; <00>; Init Memory
1>;INFO: 1024MB Bank 0
1>;INFO: 1024MB Bank 1
1>; <00>; OBP Memory Test
1>; <1f>; Init Psycho
1>; <1f>; Psycho Cntl and UPA Reg Test
1>; <1f>; Psycho DMA Scoreboard Reg Test
1>; <1f>; Psycho Perf Cntl Reg Test
1>; <1f>; PIO Decoder and BCT Test
1>; <1f>; PCI Byte Enable Test
1>; <1f>; Counter/Timer Limit Regs Test
1>; <1f>; Timer Increment Test
1>; <1f>; Timer Reload Test
1>; <1f>; Timer Periodic Test
1>; <1f>; Mondo Int Map (short) Reg Test
1>; <1f>; Mondo Int Set/Clr Reg Test
1>; <1f>; Psycho IOMMU Regs Test
1>; <1f>; Psycho IOMMU RAM NTA Test
1>; <1f>; Psycho IOMMU CAM NTA Test
1>; <1f>; Psycho IOMMU RAM Address Test
1>; <1f>; Psycho IOMMU CAM Address Test
1>; <1f>; IOMMU TLB Compare Test
1>; <1f>; IOMMU TLB Flush Test
1>; <1f>; Stream Buff A Control Reg Test
1>; <1f>; Psycho ScacheA Page Tag Addr Test
1>; <1f>; Psycho ScacheA Line Tag Addr Test
1>; <1f>; Psycho ScacheA RAM Addr Test
1>; <1f>; Psycho ScacheA Page Tag NTA Test
1>; <1f>; Psycho ScacheA Line Tag NTA Test
1>; <1f>; Psycho ScacheA Err Status NTA Test
1>; <1f>; Psycho ScacheA RAM NTA Test
1>; <1f>; Stream Buff B Control Reg Test
1>; <1f>; Psycho ScacheB Page Tag Addr Test
1>; <1f>; Psycho ScacheB Line Tag Addr Test
1>; <1f>; Psycho ScacheB RAM Addr Test
1>; <1f>; Psycho ScacheB Page Tag NTA Test
1>; <1f>; Psycho ScacheB Line Tag NTA Test
1>; <1f>; Psycho ScacheB Err Status NTA Test
1>; <1f>; Psycho ScacheB RAM NTA Test
1>; <1f>; PBMA PCI Config Space Regs Test
1>; <1f>; PBMA Control/Status Reg Test
1>; <1f>; PBMA Diag Reg Test
1>; <1f>; PBMB PCI Config Space Regs Test
1>; <1f>; PBMB Control/Status Reg Test
1>; <1f>; PBMB Diag Reg Test
1>; <1f>; Consist DMA Rd, IOMMU miss Lpbk Test
1>; <04>; Init Psycho
1>; <04>; Psycho Cntl and UPA Reg Test
1>; <04>; Psycho DMA Scoreboard Reg Test
1>; <04>; Psycho Perf Cntl Reg Test
1>; <04>; PIO Decoder and BCT Test
1>; <04>; PCI Byte Enable Test
1>; <04>; PBMA PCI Config Space Regs Test
1>; <04>; PBMA Control/Status Reg Test
1>; <04>; PBMA Diag Reg Test
1>; <04>; PBMB PCI Config Space Regs Test
1>; <04>; PBMB Diag Reg Test
1>; <04>; Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1>; <04>; Consist DMA Rd, IOMMU miss Lpbk Test
1>; <06>; Init Psycho
1>; <06>; Psycho Cntl and UPA Reg Test
1>; <06>; Psycho DMA Scoreboard Reg Test
1>; <06>; Psycho Perf Cntl Reg Test
1>; <06>; PIO Decoder and BCT Test
1>; <06>; PCI Byte Enable Test
1>; <06>; PBMA PCI Config Space Regs Test
1>; <06>; PBMA Control/Status Reg Test
1>; <06>; PBMA Diag Reg Test
1>; <06>; PBMB PCI Config Space Regs Test
1>; <06>; PBMB Diag Reg Test
1>; <06>; Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1>; <06>; Consist DMA Rd, IOMMU miss Lpbk Test
1>;STATUS=PASSED
Power On Selftest Completed
Status = 0000.0000.0000.0000 ffff.ffff.f00b.4b60 ffdf.ffff.0bd1.1111
POST Reset
CPU1 has assumed the role of Boot CPU
@(#) Sun Ultra 450 3.18 Version 0 created 2000/05/26 05:51
Offline: CPU0 (MD'ed)
Online: CPU1 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Online: CPU2 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Online: CPU3 Ultra-II (v10.0) 4:1 4096KB 2-2 ECache MCap 7
Motherboard DTAG SRAMs support up to 8192KB of ECache per CPU Module
Setting system ECache size to 4096KB
Clearing DTAGS...Done
Auxio Level = 0000.0000.0000.0005
Clearing E-Cache Tags...Done
Clearing I/D TLBs...Done
Probing Memory...Done
HiMem base = 0000.0000.0000.0000 size = 0000.0000.8000.0000
Clearing Memory...including Unix Retained Memory...Done
MMUs ON
Copying ROM to RAM...Done
RAM CRC = 0000.0000.c1c1.2aab; ROM CRC = 0000.0000.c1c1.2aab
Decompressing into Memory...0000.0000.0004.4a1c (275KB)...Done
Size = 0000.0000.0008.3930 (527KB)
Starting Forth kernel at 0000.0000.f005.8c5c
ttya initialized
Memory in 2 - way interleave configuration
...Bank #0 256 + 256 + 256 + 256 : 1024 MB
...Bank #1 256 + 256 + 256 + 256 : 1024 MB [Available 2048MB @ 0 ]
...Bank #2 0 + 0 + 0 + 0 : 0 MB [Not In Use]
...Bank #3 0 + 0 + 0 + 0 : 0 MB [Not In Use]
Programming memory controller for 10ns/100MHz UPA timing
Environmental monitor: enabled
Probing Floppy: drive detected on ID0
Probing Audio: audio codec not present
rootdisk /pci@1f,4000/scsi@3/disk@1,0
mirrordisk /pci@6,4000/scsi@4/disk@1,0
disk /pci@1f,4000/scsi@3/disk@0,0
disk0 /pci@1f,4000/scsi@3/disk@0,0
disk1 /pci@1f,4000/scsi@3/disk@1,0
disk2 /pci@1f,4000/scsi@3/disk@2,0
disk3 /pci@1f,4000/scsi@3/disk@3,0
scsi /pci@1f,4000/scsi@3
diskx0 /pci@1f,4000/scsi@2/disk@0,0
More [<space>;,<cr>;,q,n,p,c] ?作者: lisuit 时间: 2005-01-13 09:53 标题: 请教sun服务器启动的问题 try set-defaults作者: syfen 时间: 2005-01-13 10:59 标题: 请教sun服务器启动的问题 set-defaults可以了。作者: syfen 时间: 2005-01-13 12:52 标题: 请教sun服务器启动的问题 ttya-ignore-cd=flase
.obp-flags=193
.obp-state=5
set-default改变的只是这三项,不知道哪个是导致这个现象的呢?作者: lisuit 时间: 2005-01-13 13:36 标题: 请教sun服务器启动的问题 set-defaults not only change the obp parameter but also all obp setting to default.
maybe you have some other content in your nvram.作者: syfen 时间: 2005-01-13 13:45 标题: 请教sun服务器启动的问题 lisuit,3ks