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本帖最后由 bears冗 于 2010-03-04 09:33 编辑
职位一
Senior Design Engineer for Video Codec
Preferred Experience:
- Major in EE and have Master degree or higher
- 3 years beyond working experience on ASIC design
- Must have strong background on video encoding/decoding algorithms
- Must be proficient in Verilog coding, debugging and modeling
- Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
- Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
- Must be familiar with verification methodologies for from block level to SoC level.
- Should be familiar with shell/perl/tcl programming in linux OS.
- Should be familiar with P&R and Manufacture tech.
- Good English hearing, speaking, reading and writing capabilities.
- Will be a big plus if having tape‐out experience.
- Will be a plus if having C/C++, matlab experience.
5年以上，另有staff职位
职位二
Sr/MTS ASIC Design/Integration Engineer
PREFERRED EXPERIENCE:
- MSEE or PhD and CGPA of 8.0 out of 10.0 or higher with minimum 2-3 years of ASIC design and integration experience is required.
- Familiar with complex high speed ASIC Design process.
- Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design is a plus.
- Relevant experience in bus protocol USB/PCI/PCIE design is a plus.
- Relevant experience in chip level design/integration, DFT, memBIST, Memory Compiler, STA is a plus.
- Strong logic design, verification and debugging skills.
- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and C/C++ programming languages, CMOS transistors and circuits is optional.
- Good communications skills and ability and desire to work as a team player are a must.
职位三
Sr. /Jr. ASIC Design Verification Engineer
PREFERRED EXPERIENCE:
- MSEE or PhD and CGPA of 8.0 out of 10.0 or higher are required.
- Familiar with complex high speed ASIC Design process.
- Strong C/C++/System Verilog and HDL/RTL programming skills is a must.
- Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design and bus protocol PCIE is a plus.
- Strong logic analysis, verification, debugging and problem-solving skills.
- Relevant experience in Design for verification (Assertion Based Verification, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) is a plus.
- Relevant experience in Hardware emulation, System Performance modeling and analysis is an asset.
- Good communications skills and ability and desire to work as a team player are a must.
5年以上另有staff职位
职位四
Sr. Physical Design Engineer
PREFERRED EXPERIENCE:
- PhD with 1+ years of industrial experience or MSEE with 3+ years of industrial experience in ASIC design
- Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure.
- Successfully gone through complete product development cycle. Good analytical and debugging skills
- Good listening, writing and speaking English.
- Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
- Familiar with Back-End (physical design) EDA tools (synopsys, cadence, magma)
- Familiar with Front-End EDA tools or circuit design is a plus
- Familiar with Unix/Linux environment and good at scripts.
8年以上另有manager职位
职位五
DFT Engineer
PREFERRED EXPERIENCE:
- Master of EE or above. New graduate considered.
- Knowledge of Digital design, IC design methodology and Concepts of design for test.
- Be familiar with verilog language
- Be familiar with Unix and TCL, shell , Perl scripts.
- Strong debug abilities.
- Good English communication skills
- Self-motivated and good team player.
8年以上另有manager职位
以上职位base地点均在上海
需求量比较大
有兴趣的可直接发简历到邮箱，或MSN沟通
rongchris@hotmail.com
[ 本帖最后由 bears冗 于 2010-1-20 13:17 编辑 ] |
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发表于 2009-11-02 11:36