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本帖最后由 qianxia0_ 于 2011-11-29 10:25 编辑
Hardware Power On
@(#)OBP 4.15.4 2004/12/02 08:05 Sun Fire 4XX
System is initializing with diag-switch? overrides.
Online: CPU1 CPU3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done
Probing core system FRUs..
Probing Centerplane....part# 501-6790-01 serial# 001916
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 063125
Probing System RSC.....part# 501-5856-06 serial# 254539
Probing PwrDistBoard...part# 375-3006-05 serial# M75005
Probing PowerSupply0...part# 300-1480-05 serial# N49943
Probing PowerSupply1...part# 300-1480-05 serial# N44500
Probing FCAL BPlane0...part# 501-5822-04 serial# 061502
Probing GPTwo Slot A...No module detected
Probing GPTwo Slot B...part# 501-6164-02 serial# 096133
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
CPU rated speed 1200MHz; ECache 8MB 3.3ns Done
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU1 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU3 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00 Done
Setting system speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP 4.15.4 2004/12/02 08:05 Sun Fire 4XX
System is initializing with diag-switch? overrides.
Online: CPU1 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: *CPU3 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Executing POST w/%o0 = 0000.0800.0101.4041
1:0>
1:0>@(#) Sun Fire[TM] V480/V490 POST 4.15.4 2004/11/23 12:48
/dat/fw/common-source/firmware_re/post/post-build-4.15.4/Camelot/cstone/integrated (firmware_re)
1:0>Copyright 2004 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
1:0>Jump from OBP-> OST.
1:0>Diag level set to MAX.
1:0>Verbosity level set to NORMAL.
1:0>
1:0>Start selftest...
1:0>CPUs present in system: 1:0 3:0
1:0>Test CPU(s)....Done
1:0>Init Scan/I2C....Done
1:0>Basic Memory Test....\
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000032
Trap PC ffffffff.f012190c
Trap Level 00000000.00000001
AFSR 00100004.00000060
AFAR 00000030.001b0040
1:0>END_WARNING
/
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000032
Trap PC ffffffff.f012190c
Trap Level 00000000.00000001
AFSR 00100004.00000060
AFAR 00000031.001b0040
1:0>END_WARNING
\
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000032
Trap PC ffffffff.f012190c
Trap Level 00000000.00000001
AFSR 00100004.00000060
AFAR 00000032.001b0040
1:0>END_WARNING
/
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
Trap Type 00000000.00000032
Trap PC ffffffff.f012190c
Trap Level 00000000.00000001
AFSR 00100004.00000060
AFAR 00000033.001b0040
1:0>END_WARNING
\
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG =
*** Test Failed!! ***
1:0>END_ERROR
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = ERROR: Memory error on master CPU, rolling over to new master.
1:0>END_ERROR
|
3:0>Start selftest...
3:0>CPUs present in system: 1:0 3:0
3:0>Test CPU(s)....Done
3:0>Init Scan/I2C....Done
3:0>Basic Memory Test....|
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = No Memory Detected
3:0>END_ERROR
/
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG =
*** Test Failed!! ***
3:0>END_ERROR
3:0>
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = ERROR: Memory error on master CPU, rolling over to new master.
3:0>END_ERROR
Done
3:0>ERROR: No good CPUs left! Calling debug menu.
3:0> 0 Peek/Poke interface
3:0> 1 Dump DAR Error Bits
3:0> 2 Dump Scan Chain
3:0> 3 Dump CPU Regs
3:0> 4 Dump BBC Regs
3:0> 5 Dump Mem Controller Regs
3:0> 6 Dump Valid DMMU entries
3:0> 7 Dump IMMU entries
3:0> 8 Dump Struct Info
3:0> 9 Dump Mailbox
3:0> a Dump IO-Bridge regs unit 0
3:0> b Dump IO-Bridge regs unit 1
3:0> c Allow other CPUs to print
3:0> d Do soft reset
3:0> ? Help
3:0>
3:0>Selection:
<*>
Hardware Power On
@(#)OBP 4.15.4 2004/12/02 08:05 Sun Fire 4XX
System is initializing with diag-switch? overrides.
Online: CPU0 CPU2*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done
Probing core system FRUs..
Probing Centerplane....part# 501-6790-01 serial# 001916
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 063125
Probing System RSC.....part# 501-5856-06 serial# 254539
Probing PwrDistBoard...part# 375-3006-05 serial# M75005
Probing PowerSupply0...part# 300-1480-05 serial# N49943
Probing PowerSupply1...part# 300-1480-05 serial# N44500
Probing FCAL BPlane0...part# 501-5822-04 serial# 061502
Probing GPTwo Slot A...part# 501-6164-02 serial# 096133
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
CPU rated speed 1200MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...No module detected Done
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU0 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU2 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00 Done
Setting system speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP 4.15.4 2004/12/02 08:05 Sun Fire 4XX
System is initializing with diag-switch? overrides.
Online: CPU0 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: *CPU2 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Executing POST w/%o0 = 0000.0800.0101.4041
0:0>
0:0>@(#) Sun Fire[TM] V480/V490 POST 4.15.4 2004/11/23 12:48
/dat/fw/common-source/firmware_re/post/post-build-4.15.4/Camelot/cstone/integrated (firmware_re)
0:0>Copyright 2004 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0:0>Jump from OBP-> OST.
0:0>Diag level set to MAX.
0:0>Verbosity level set to NORMAL.
0:0>
0:0>Start selftest...
0:0>CPUs present in system: 0:0 2:0
0:0>Test CPU(s)....Done
0:0>Init Scan/I2C....\
第一个是插slotB的 第二个是插slotA的 现在怎么搞啊? |
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