MIPS下的cache/uncache访问的一点想法

yidou

有同事提到在客户平台下访问cache地址的问题.
Q: XXX used cached reads from the FLASH to read back some data, but found that sometimes they read the wrong data. I'm checking with them to see if the use cached writes to FLASH also.

In our FW, we use uncached writes to FLASH. Can you please help me understand why we need to use uncached writes (or reads) to the FLASH? Is there a possibility that the data in the cache is not written to FLASH if we use cached access?


A: For flash device, cached write/erase command sequence may cause problems.

For example:
A common sector erase command sequence without cache is:
ADDR: 555 DATA:AA
ADDR: AAA DATA:55
ADDR: 555  DATA:80
ADDR: 555 DATA:AA
ADDR: AAA DATA:55
ADDR: SA DATA:30

Whitin cache , it may look like:
ADDR: 555 DATA:AA
ADDR: AAA DATA:55
//ADDR: 555  DATA:80   => Addr 555 is cache hit and DATA is changed to 80
//ADDR: 555 DATA:AA   => Addr 555 is cache hit and DATA is changed to AA
//ADDR: AAA DATA:55   => Addr AAA is cache hit and DATA is unchanged
ADDR: SA DATA:30

Then the sequence becomes:
ADDR: 555 DATA:AA
ADDR: AAA DATA:55
ADDR: SA DATA:30

In result the above sequence in cache becomes an invalid erase sequence. The same as other flash command sequences beyond one cycle.

[结论]可见, 对于这种有严格时序要求的IO访问, 只能访问uncache地址.

[ 本帖最后由 yidou 于 2009-4-28 11:27 编辑 ]

sep

我们平台也是mips，将framebuffer映射到cache上，再调用flush cache函数将cache上的数据冲洗到framebuffer中。如果要保持cache和IO数据的一致性，应该实现这样的类似接口

kentzhou

嗯，看到有一段和这个相关的
The kseg1 region is the only chunk of the memory map that is guaranteed to behave properly from system reset; that’s why the after-reset
starting point (0xBFC0.0000) lies within it. You will therefore use this region to access your initial program ROM,and most people use it for I/O registers.
----《 see mips run》