帮忙看下哪儿的问题?E3500POST信息

jsc_flying

3,0>    Ecache Quick Verify\r\n\r\n3,0>    Ecache Init\r\n\r\n3,1>    Ecache Quick Verify\r\n\r\n3,1>    Ecache Init\r\n\r\n3,0>    Ecache RAM\r\n\r\n3,1>    Ecache RAM\r\n\r\n3,0>    Ecache Address Line\r\n\r\n3,0>    Configure Ecache Limit\r\n\r\n3,0>Ecache Size = 00800000,  Limited to 00800000 \r\n\r\n3,0>Board 3 FPU Functional Test\r\n\r\n3,0>    FPU Enable\r\n\r\n3,0>Board 3 Board Master Select Test\r\n\r\n3,0>    Selecting a Board Master\r\n\r\n3,0>Board 3 FireHose Devices Test\r\n\r\n3,1>    Ecache Address Line\r\n\r\n3,1>    Configure Ecache Limit\r\n\r\n3,1>Ecache Size = 00800000,  Limited to 00800000 \r\n\r\n3,1>Board 3 FPU Functional Test\r\n\r\n3,1>    FPU Enable\r\n\r\n3,1>Board 3 Board Master Select Test\r\n\r\n3,1>    Selecting a Board Master\r\n\r\n3,0>Board 3 Address Controller Test\r\n\r\n3,0>    AC Initialization\r\n\r\n3,0>    AC DTAG Init\r\n\r\n3,0>Board 3 Dual Tags Test\r\n\r\n3,0>    AC DTAG Init\r\n\r\n3,0>Board 3 FireHose Controller Test\r\n\r\n3,0>    FHC Initialization\r\n\r\n3,0>Board 3 JTAG Test\r\n\r\n3,0>    Verify System Board Scan Ring\r\n\r\n3,0>Board 3 Centerplane Test\r\n\r\n3,0>    Centerplane Join\r\n\r\n3,0>Setting JTAG Master\r\n\r\n3,0>Clear JTAG Master\r\n\r\n3,0>Board 3 Setup Cache Size Test\r\n\r\n3,0>    Setting Up Cache Size\r\n\r\n3,0>Board 3 System Master Select Test\r\n\r\n3,0>    Setting System Master\r\n\r\n3,0>POST Master Selected (JTAG,CENTRAL)\r\n\r\n3,0>Board 16 Clock Board Test\r\n\r\n3,0>    Clock Board Initialization\r\n\r\n3,0>    Clock Board Temperature Check\r\n\r\n3,0>Board 16 Clock Board Serial Ports Test\r\n\r\n3,0>Board 16 NVRAM Devices Test\r\n\r\n3,0>    M48T59 (TOD) Init\r\n\r\n3,0>Board 3 System Board Probe  Test\r\n\r\n3,0>    Probing all CPU/Memory BDA\r\n\r\n3,0>    Probing System Boards\r\n\r\n3,0>    Probing CPU Module JTAG Rings\r\n\r\n3,0>Setting System Clock Frequency\r\n\r\n3,0>        CPU Module mid 6 Checked in OK (speed code = 3)\r\n\r\n3,0>        CPU mid 7 Version=00170011.a0000507\r\n\r\n3,0>        CPU Module mid 7 Checked in OK (speed code = 3)\r\n\r\n3,0> ******** Clock Reset - retesting \r\n\r\n3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400\r\n\r\n3,0>\r\n\r\n3,0>@(#) POST 3.9.26 2000/05/09 19:13\r\n\r\n3,1>\r\n\r\n3,0>Copyright 2000 Sun Microsystems, Inc. All rights reserved.\r\n\r\n3,1>@(#) POST 3.9.26 2000/05/09 19:13\r\n\r\n3,0>\r\n\r\n    SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK a0\r\n\r\n3,1>Copyright 2000 Sun Microsystems, Inc. All rights reserved.\r\n\r\n3,0>Board 3 CPU FPROM Test\r\n\r\n3,1>\r\n\r\n    SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK a0\r\n\r\n3,0>    CPU/Memory Board FPROM Checksum Test\r\n\r\n3,1>Board 3 CPU FPROM Test\r\n\r\n3,1>    CPU/Memory Board FPROM Checksum Test\r\n\r\n3,0>Board 3 Basic CPU Test\r\n\r\n3,0>    FPU Registers and Data Path Test\r\n\r\n3,0>    Instruction Cache Tag RAM Test\r\n\r\n3,1>Board 3 Basic CPU Test\r\n\r\n3,1>    FPU Registers and Data Path Test\r\n\r\n3,1>    Instruction Cache Tag RAM Test\r\n\r\n3,0>    Instruction Cache Instruction RAM Test\r\n\r\n3,1>    Instruction Cache Instruction RAM Test\r\n\r\n3,0>    Instruction Cache Next Field RAM Test\r\n\r\n3,1>    Instruction Cache Next Field RAM Test\r\n\r\n3,0>    Instruction Cache Pre-decode RAM Test\r\n\r\n3,1>    Instruction Cache Pre-decode RAM Test\r\n\r\n3,0>    Data Cache RAM Test\r\n\r\n3,1>    Data Cache RAM Test\r\n\r\n3,0>    Data Cache Tags Test\r\n\r\n3,1>    Data Cache Tags Test\r\n\r\n3,0>    DMMU Registers Access Test\r\n\r\n3,0>    DMMU TLB DATA RAM Access Test\r\n\r\n3,0>    DMMU TLB TAGS Access Test\r\n\r\n3,0>    IMMU Registers Access Test\r\n\r\n3,1>    DMMU Registers Access Test\r\n\r\n3,0>    IMMU TLB DATA RAM Access Test\r\n\r\n3,1>    DMMU TLB DATA RAM Access Test\r\n\r\n3,0>    IMMU TLB TAGS Access Test\r\n\r\n3,1>    DMMU TLB TAGS Access Test\r\n\r\n3,0>    Set CPU UPA Config and Init SDB Data\r\n\r\n3,0>        SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n\r\n3,1>    IMMU Registers Access Test\r\n\r\n3,0>Board 3 MMU Enable Test\r\n\r\n3,0>    DMMU Init\r\n\r\n3,0>    IMMU Init\r\n\r\n3,1>    IMMU TLB DATA RAM Access Test\r\n\r\n3,0>    Mapping Selftest Enabling MMUs\r\n\r\n3,0>Board 3 Ecache Test\r\n\r\n3,0>    Ecache Probe\r\n\r\n3,1>    IMMU TLB TAGS Access Test\r\n\r\n3,0>    Ecache Tags\r\n\r\n3,1>    Set CPU UPA Config and Init SDB Data\r\n\r\n3,1>        SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n\r\n3,1>Board 3 MMU Enable Test\r\n\r\n3,1>    DMMU Init\r\n\r\n3,1>    IMMU Init\r\n\r\n3,1>    Mapping Selftest Enabling MMUs\r\n\r\n3,1>Board 3 Ecache Test\r\n\r\n3,1>    Ecache Probe\r\n\r\n3,1>    Ecache Tags\r\n\r\n3,0>    Ecache Quick Verify\r\n\r\n3,1>    Ecache Quick Verify\r\n\r\n3,0>    Ecache Init\r\n\r\n3,1>    Ecache Init\r\n\r\n3,0>    Ecache RAM\r\n\r\n3,1>    Ecache RAM\r\n\r\n3,0>    Ecache 6N RAM Pattern Test\r\n\r\n3,1>    Ecache 6N RAM Pattern Test\r\n\r\n3,0>    Ecache Address Line\r\n\r\n3,0>    Configure Ecache Limit\r\n\r\n3,0>Ecache Size = 00800000,  Limited to 00800000 \r\n\r\n3,0>Board 3 FPU Functional Test\r\n\r\n3,0>    FPU Enable\r\n\r\n3,0>Board 3 Board Master Select Test\r\n\r\n3,0>    Selecting a Board Master\r\n\r\n3,1>    Ecache Address Line\r\n\r\n3,0>Board 3 FireHose Devices Test\r\n\r\n3,0>    PROM Datapath Test\r\n\r\n3,1>    Configure Ecache Limit\r\n\r\n3,0>    FHC CPU SRAM Test\r\n\r\n3,1>Ecache Size = 00800000,  Limited to 00800000 \r\n\r\n3,1>Board 3 FPU Functional Test\r\n\r\n3,1>    FPU Enable\r\n\r\n3,1>Board 3 Board Master Select Test\r\n\r\n3,1>    Selecting a Board Master\r\n\r\n3,0>Board 3 Address Controller Test\r\n\r\n3,0>    AC Registers Test\r\n\r\n3,0>    AC Initialization\r\n\r\n3,0>    Memory Registers  Test\r\n\r\n3,0>    Memory Registers Initialization Test\r\n\r\n3,0>    AC DTAG Init\r\n\r\n3,0>Board 3 Dual Tags Test\r\n\r\n3,0>    AC DTAG Test\r\n\r\n3,0>    AC DTAG Init\r\n\r\n3,0>Board 3 FireHose Controller Test\r\n\r\n3,0>    FHC Initialization\r\n\r\n3,0>Board 3 JTAG Test\r\n\r\n3,0>    Verify System Board Scan Ring\r\n\r\n3,0>Board 3 Centerplane Test\r\n\r\n3,0>    Centerplane and Arbiter Check Test\r\n\r\n3,0>Setting JTAG Master\r\n\r\n3,0>Clear JTAG Master\r\n\r\n3,0>    Centerplane Join\r\n\r\n3,0>Setting JTAG Master\r\n\r\n3,0>Clear JTAG Master\r\n\r\n3,0>Board 3 Setup Cache Size Test\r\n\r\n3,0>    Setting Up Cache Size\r\n\r\n3,0>Board 3 System Master Select Test\r\n\r\n3,0>    Setting System Master\r\n\r\n3,0>POST Master Selected (JTAG,CENTRAL)\r\n\r\n3,0>Board 16 Clock Board Test\r\n\r\n3,0>    Clock Board Registers Test\r\n\r\n3,0>    Clock Board Initialization\r\n\r\n3,0>    Clock Board Temperature Check\r\n\r\n3,0>Board 16 Clock Board Serial Ports Test\r\n\r\n3,0>    85C30 Register Test\r\n\r\n3,0>    85C30 Serial Ports Test\r\n\r\n3,0>        Keyboard Loopback\r\n\r\n3,0>        Mouse Loopback\r\n\r\n3,0>        Serial Port B Loopback\r\n\r\n3,0>        Remote Serial Port A Loopback\r\n\r\n3,0>        Remote Serial Port B Loopback\r\n\r\n3,0>Board 16 NVRAM Devices Test\r\n\r\n3,0>    M48T59 (TOD) Init\r\n\r\n3,0>    M48T59 (TOD) Functional Part 1 Test\r\n\r\n3,0>    NVRAM(Non-Destructive) Test\r\n\r\n3,0>Board 3 System Board Probe  Test\r\n\r\n3,0>    Probing all CPU/Memory BDA\r\n\r\n3,0>    Probing System Boards\r\n\r\n3,0>    Probing CPU Module JTAG Rings\r\n\r\n3,0>Setting System Clock Frequency\r\n\r\n3,0>        CPU Module mid 6 Checked in OK (speed code = 3)\r\n\r\n3,0>        CPU mid 7 Version=00170011.a0000507\r\n\r\n3,0>        CPU Module mid 7 Checked in OK (speed code = 3)\r\n\r\n3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400\r\n\r\n3,0>TESTING BOARD 1\r\n\r\n3,0>Board 1 JTAG Test\r\n\r\n3,0>    Verify System Board Scan Ring\r\n\r\n3,0>Board 1 Centerplane Test\r\n\r\n3,0>    Centerplane Check\r\n\r\n3,0>Board 1 Address Controller Test\r\n\r\n3,0>    AC Registers Test\r\n\r\n3,0>    AC Initialization\r\n\r\n3,0>Setting Freq to 25MHZ\r\n\r\n3,0>    Memory Registers  Test\r\n\r\n3,0>    Memory Registers Initialization Test\r\n\r\n3,0>    AC DTAG Init\r\n\r\n3,0>Board 1 FireHose Controller Test\r\n\r\n3,0>    FHC Initialization\r\n\r\n3,0>Board 1 NVRAM Devices Test\r\n\r\n3,0>    M48T59 (TOD) Init\r\n\r\n3,0>    M48T59 (TOD) Functional Part 1 Test\r\n\r\n3,0>    NVRAM(Non-Destructive) Test\r\n\r\n3,0>Re-mapping to Local Device Space\r\n\r\n3,0>Begin Central Space Serial Port access\r\n\r\n3,0>Enable AC Control Parity\r\n\r\n3,0>Hotplug Trigger Test\r\n\r\n3,0>        ERROR: TRIG_CHK asserted in Clock Board - Hint: Board(s) may not be properly seated\r\n\r\n3,0>Board 3 Cross Calls Test\r\n\r\n3,0>    Cross Calls Test\r\n\r\n3,0>Displaying PROM Versions\r\n\r\n3,0>Slot 1 IO Type 4    FCODE 1.8.30 2002/10/25 14:02  iPOST 3.4.30 2002/10/25 14:03\r\n\r\n3,0>Slot 3 CPU/Memory   OBP   3.2.26 2000/5/9 19:07  POST  3.9.26 2000/5/9 19:13\r\n\r\n3,0>Board 3 Environmental Probe Test\r\n\r\n3,0>    Environmental Probe\r\n\r\n3,0>Checking Power Supply Configuration\r\n\r\n3,0>Power is more than adequate, load 2 ps 2\r\n\r\n3,0>Reconfig memory due to POR or CLOCK RESET\r\n\r\n3,0>Reconfig memory due to DIAG_LEVEL\r\n\r\n3,0>Board 3 Probing Memory SIMMS Test\r\n\r\n3,0>    Probe SIMMID\r\n\r\n3,0>        Populated Memory Bank Status\r\n\r\n3,0>                bd #        Size        Address        Way        Status\r\n\r\n3,0>                3        1024                        Normal\r\n\r\n3,0>Board 3 Memory Configuration Test\r\n\r\n3,0>    Memory Interleaving\r\n\r\n3,0>        Total banks with 8MB SIMMs = 0\r\n\r\n3,0>        Total banks with 32MB SIMMs = 0\r\n\r\n3,0>        Total banks with 128MB SIMMs = 1\r\n\r\n3,0>        Total banks with 256MB SIMMs = 0\r\n\r\n3,0>        Overall memory default speed = 60ns\r\n\r\n3,0>Do OPTIMAL INTLV\r\n\r\n3,0>        Board 3 AC rev 5 RCTIME = 1 (Tras 71)\r\n\r\n3,0>    Memory Refresh Enable\r\n\r\n3,0>Board 3 SIMMs Test\r\n\r\n3,0>    MP Memory SIMM Clear Test\r\n\r\n3,0>        Memory Size is 1024Mbytes\r\n\r\n3,0>          CPU MID 7 clearing 00000000.00004000 to 00000000.20000000\r\n\r\n3,0>          CPU MID 6 clearing 00000000.20000000 to 00000000.40000000\r\n\r\n3,0>          CPU MID 6 clearing 00000000.00000000 to 00000000.00004000\r\n\r\n3,0>    Memory Walking Rows and Columns Test\r\n\r\n3,0>    MP Memory SIMM (6N RAM Patterns) Test\r\n\r\n3,0>        Memory Size is 1024Mbytes\r\n\r\n3,0>          CPU MID 7 testing 00000000.00000000 to 00000000.20000000\r\n\r\n3,0>          CPU MID 6 testing 00000000.20000000 to 00000000.40000000\r\n\r\n3,0>    MP Memory SIMM (moving inverse) Test\r\n\r\n3,0>        Memory Size is 1024Mbytes\r\n\r\n3,0>          CPU MID 7 testing 00000000.00000000 to 00000000.20000000\r\n\r\n3,0>          CPU MID 6 testing 00000000.20000000 to 00000000.40000000\r\n\r\n3,0>Slave CPU Functional Tests\r\n\r\n3,0>         Slave CPU MID 7 started\r\n\r\n3,1>Board 3 Functional CPU 1 Test\r\n\r\n3,1>    Dcache Init\r\n\r\n3,1>    Dcache Enable Test\r\n\r\n3,1>    Dcache Functionality Test\r\n\r\n3,1>    Ecache Stress Test\r\n\r\n3,1>    Ecache Functional Test\r\n\r\n3,1>    CPU Dispatch (Multi-Scalar) Test\r\n\r\n3,1>    SPARC Atomic Instructions Test\r\n\r\n3,1>    SPARC Prefetch Instructions Test\r\n\r\n3,1>    CPU Softint Registers and Interrupts Test\r\n\r\n3,1>    Uni-Processor Cache Coherence Test\r\n\r\n3,1>    Branch Memory Test\r\n\r\n3,1>    SDB ECC CE Test\r\n\r\n3,1>    SDB ECC Uncorrectable Test\r\n\r\n3,1>    FPU Instruction Test\r\n\r\n3,0>Board 3 Functional CPU 0 Test\r\n\r\n3,0>    Dcache Init\r\n\r\n3,0>    Dcache Enable Test\r\n\r\n3,0>    Dcache Functionality Test\r\n\r\n3,0>    Ecache Stress Test\r\n\r\n3,0>    Ecache Functional Test\r\n\r\n3,0>    CPU Dispatch (Multi-Scalar) Test\r\n\r\n3,0>    SPARC Atomic Instructions Test\r\n\r\n3,0>    SPARC Prefetch Instructions Test\r\n\r\n3,0>    CPU Softint Registers and Interrupts Test\r\n\r\n3,0>    Uni-Processor Cache Coherence Test\r\n\r\n3,0>    Branch Memory Test\r\n\r\n3,0>    SDB ECC CE Test\r\n\r\n3,0>    SDB ECC Uncorrectable Test\r\n\r\n3,0>    FPU Instruction Test\r\n\r\n3,0>TESTING IO BOARD 1\r\n\r\n3,0>Board 1 I/O FPROM Test\r\n\r\n3,0>    I/O Board EPROM checksum Test\r\n\r\n3,0>@(#) iPOST 3.4.30 2002/10/25 14:03\r\n\r\n3,0> TESTING IO BOARD 1 ASICs\r\n\r\n3,0> TESTING SysIO Port 0\r\n\r\n3,0>Board 1 SysIO Registers Test\r\n\r\n3,0>    SysIO Register Initialization\r\n\r\n3,0>    IOMMU Registers and RAM Test\r\n\r\n3,0>    Streaming Buffer Registers and RAM Test\r\n\r\n3,0>    SBus Control and Config Registers Test\r\n\r\n3,0>    SysIO RAM Initialization\r\n\r\n3,0>Board 1 SysIO Functional Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers\r\n\r\n3,0>    SysIO Interrupts  Test\r\n\r\n3,0>    SysIO Timers/Counters Test\r\n\r\n3,0>    IOMMU Virtual Address TLB Tag Compare Test\r\n\r\n3,0>    Streaming Buffer Flush Test\r\n\r\n3,0>    DMA Merge Buffer Test\r\n\r\n3,0>    SYSIO ECC Correctable Test\r\n\r\n3,0>    SYSIO ECC UnCorrectable Test\r\n\r\n3,0>    SysIO Sbus Probe Test\r\n\r\n3,0>    SysIO Register Initialization Test\r\n\r\n3,0>    SysIO RAM Initialization Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers Test\r\n\r\n3,0>Board 1 OnBoard IO Chipset (SOC) Test\r\n\r\n3,0>    SOC SRAM Test\r\n\r\n3,0>    SOC Registers Test\r\n\r\n3,0>    SOC Interrupt Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers Test\r\n\r\n3,0> TESTING SysIO Port 1\r\n\r\n3,0>Board 1 SysIO Registers Test\r\n\r\n3,0>    SysIO Register Initialization\r\n\r\n3,0>    IOMMU Registers and RAM Test\r\n\r\n3,0>    Streaming Buffer Registers and RAM Test\r\n\r\n3,0>    SBus Control and Config Registers Test\r\n\r\n3,0>    SysIO RAM Initialization\r\n\r\n3,0>Board 1 SysIO Functional Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers\r\n\r\n3,0>    SysIO Interrupts  Test\r\n\r\n3,0>    SysIO Timers/Counters Test\r\n\r\n3,0>    IOMMU Virtual Address TLB Tag Compare Test\r\n\r\n3,0>    Streaming Buffer Flush Test\r\n\r\n3,0>    DMA Merge Buffer Test\r\n\r\n3,0>    SYSIO ECC Correctable Test\r\n\r\n3,0>    SYSIO ECC UnCorrectable Test\r\n\r\n3,0>    SysIO Sbus Probe Test\r\n\r\n3,0>    SysIO Register Initialization Test\r\n\r\n3,0>    SysIO RAM Initialization Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers Test\r\n\r\n3,0>Board 1 OnBoard IO Chipset (FEPS) Test\r\n\r\n3,0>    FAS366 Registers Test\r\n\r\n3,0>    ESP FAS366 DVMA burst mode read/write Test\r\n\r\n3,0>    FAS366 FIFO TO DMA Test\r\n\r\n3,0>    DMA TO FAS366 FIFO Test\r\n\r\n3,0>    FEPS (Ethernet) Registers Test\r\n\r\n3,0>    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test\r\n\r\n3,0>    SysIO Register Initialization Test\r\n\r\n3,0>    SysIO RAM Initialization Test\r\n\r\n3,0>    Clear Interrupt Map and State Registers Test\r\n\r\n3,0>IO BOARD 1 TESTED\r\n\r\n3,0>SYSTEM LEVEL TESTING\r\n\r\n3,0>Board 3 Cache Coherency Test\r\n\r\n3,0>    Multi-Processor Cache Coherence Test\r\n\r\n3,0>        Testing CPU MID 7\r\n\r\n3,0>Probing for Disk System boards\r\n\r\n3,0>Board 3 System Interrupts Test\r\n\r\n3,0>    System Interrupts Test\r\n\r\n3,0>Checking Power Supply Configuration\r\n\r\n3,0>Power is more than adequate, load 2 ps 2\r\n\r\n3,0>    Check Board Present Test\r\n\r\n3,0>    Board Present Interrupt Test\r\n\r\n3,0>POST Failed\r\n\r\n3,0>\r\n\r\n3,0>        System Board Status\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0> Slot   Board Status     Board Type      Failures\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0>  0  | Not installed  |             |\r\n\r\n3,0>  1  | Normal         |+IO Type 4   |\r\n\r\n3,0>  2  | Not installed  |             |\r\n\r\n3,0>  3  | Normal         |+CPU/Memory  |\r\n\r\n3,0>  4  | Not installed  |             |\r\n\r\n3,0>  5  | Not installed  |             |\r\n\r\n3,0>  6  | Not installed  |             |\r\n\r\n3,0>  7  | Not installed  |             |\r\n\r\n3,0>  8  | Not installed  |             |\r\n\r\n3,0>  9  | Not installed  |             |\r\n\r\n3,0> 16  | Online/failure | Clock Board | HOTPLUG_LOGIC\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0>\r\n\r\n3,0>        CPU Module Status\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0> MID  OK  Cache  Speed   Version\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0>  6 | y | 8192  |  400  | 00170011.a0000507\r\n\r\n3,0>  7 | y | 8192  |  400  | 00170011.a0000507\r\n\r\n3,0>-----------------------------------------------------------------\r\n\r\n3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400\r\n\r\n3,0>        Populated Memory Bank Status\r\n\r\n3,0>                bd #        Size        Address        Way        Status\r\n\r\n3,0>                3        1024        0        0        Normal\r\n\r\n3,0>\r\n\r\n3,0>\r\n\r\n        POST COMPLETE\r\n\r\n3,0>Entering OBP\r\n ttya initialized\r\nUsing POST\'s System Configuration\r\nSetting up memory\r\nStarting CPU ID 7 \r\nClock board TOD does not match TOD on any IO board.\r\n测试E3500,怀疑CLOCK板问题，换了板还出现此问题,

nimysun

TOD is equal to \"time of day\"\r\nRun only one command under OK prompt as the following:\r\ncopy-io-board-tod-to-clock-tod

lyh003473

检测到电源好会中断了。是不是电源的问题呀

vahmoiz

Clock board TOD does not match TOD on any IO board.是可以忽略的