- 论坛徽章:
- 0
|
ASIC DFT Engineer
Key responsibilities:
• ASIC DFT design and verification for JTAG boundary scan, scan, memory BIST and ATPG test vector generation.
• Design verification and debugging (both simulation based and C based), test coverage debugging and design automation scripting skills are required.
Requirements:
• strong problem solving skill and debugging skill.
• familiar with ASIC design flow from RTL Verilog coding, synthesis, timing to verification.
• Hands-on experience on ASIC or DFT design is a plus, but is not a requirement for new graduates.
• Verbal and written English communication skill is a must.
• MSEE/CS or equivalent, with 5+ year relevant experience, or BSEE/CS with 10+ year relevant experience. PhD degree is a plus.
• New grads or low experience but have great potential are also acceptable.
有意向请联系我，65888118——202。邮件：qinhr@e4u.cn msn: qinhuarong@hotmail.com |
|
免费注册
发表于 2007-06-11 12:48
发表于 2007-06-11 16:04
