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原帖由 bluesky_jxc 于 2008-5-3 11:29 发表
copy from 8259 spec:
"Interrupt Request Register (IRR): 8-bit register which
contains the levels requesting an interrupt to be acknowledged.
The highest request level is reset from
the IRR wh ...
多谢!
但是对于pending两个的说法,我还是有点不理解。
你说的这种情况,我觉得实际上是只pending了一个“待处理”中断,因为另一个已经在处理了。
From SDM 8.8.4:
IF more than one interrupt is generated with the same vector number, the local APIC can set the bit for the vector both in the IRR and ISR.
就是这句话说的不太清楚。
假设这样子,eflags.if=0
然后同样的vector来了三个中断,那么IRR和ISR是怎样的状态呢?
都是1,那么ISR的状态跟它本身代表的含义是不符的,或者这是一种特殊情况? |
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