mmap共享内存更新不及时

luoyan_xy

  哈哈，PPC的这个问题我也遇到过，硬件DMA跟上层共享数据的话不会自动刷新cache，当时我是在访问之前，使用flush_cache_range刷新了cache

瀚海书香

回复 11# luoyan_xy

哈哈，PPC的这个问题我也遇到过，硬件DMA跟上层共享数据的话不会自动刷新cache，当时我是在访问之前，使用flush_cache_range刷新了cache

没在PPC平台上用过。多谢分享

arm-linux-gcc

ppc是pipt的cache，所以不会出现cache alias的问题
LZ之前代码中有pgprot_noncached，于是kernel就是写的data cache，而app却是直接读的内存，所以数据不一致
而LZ后面又去掉了pgprot_noncached，于是kernel和app都是读写的data cache，而ppc又是pipt的cache，所以app和kernel都是读写的同一个cache line，因此没有问题了

tqyou85

arm-linux-gcc 发表于 2013-08-10 11:58
ppc是pipt的cache，所以不会出现cache alias的问题
LZ之前代码中有pgprot_noncached，于是kernel就是写的d ...

多谢LS大侠解答，对cache alias这些概念不是很懂，特意查了下：
Caches can be divided into 4 types, based on whether the index or tag correspond to physical or virtual addresses:

    Physically indexed, physically tagged (PIPT) caches use the physical address for both the index and the tag. While this is simple and avoids problems with aliasing, it is also slow, as the physical address must be looked up (which could involve a TLB miss and access to main memory) before that address can be looked up in the cache.

    Virtually indexed, virtually tagged (VIVT) caches use the virtual address for both the index and the tag. This caching scheme can result in much faster lookups, since the MMU doesn't need to be consulted first to determine the physical address for a given virtual address. However, VIVT suffers from aliasing problems, where several different virtual addresses may refer to the same physical address. The result is that such addresses would be cached separately despite referring to the same memory, causing coherency problems. Another problem is homonyms, where the same virtual address maps to several different physical addresses. It is not possible to distinguish these mappings by only looking at the virtual index, though potential solutions include: flushing the cache after a context switch, forcing address spaces to be non-overlapping, tagging the virtual address with an address space ID (ASID), or using physical tags. Additionally, there is a problem that virtual-to-physical mappings can change, which would require flushing cache lines, as the VAs would no longer be valid.

    Virtually indexed, physically tagged (VIPT) caches use the virtual address for the index and the physical address in the tag. The advantage over PIPT is lower latency, as the cache line can be looked up in parallel with the TLB translation, however the tag can't be compared until the physical address is available. The advantage over VIVT is that since the tag has the physical address, the cache can detect homonyms. VIPT requires more tag bits, as the index bits no longer represent the same address.

    Physically indexed, virtually tagged (PIVT) caches are only theoretical as they would basically be useless.[13]

The speed of this recurrence (the load latency) is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM.

http://en.wikipedia.org/wiki/CPU_cache#Associativity