V490 报错

fjmydfh

Configuring CPUs..........
..CMP0.0 Speed 1350MHz Ecache  8MB 3.3ns mode=5-5-5(2) 2-way
..CMP0.1 Speed 1350MHz Ecache  8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.0 Speed 1350MHz Ecache  8MB 3.3ns mode=5-5-5(2) 2-way
..CMP2.1 Speed 1350MHz Ecache  8MB 3.3ns mode=5-5-5(2) 2-way Done
<*>
CPU Configuration Reset

@(#)OBP 4.18.2 2005/06/30 07:52 Sun Fire 4XX
FATAL: All CPUs failed or disabled! Attempting recovery...
System is initializing in Service Mode.
Online:  CMP0 UltraSPARC IV  (v3.1)  9:1 1350MHz  8MB 5:1 ECache
Online: *CMP2 UltraSPARC IV  (v3.1)  9:1 1350MHz  8MB 5:1 ECache
ERROR: chkpost: Problems with I2C; forcing POST call w/%o0 = 0000.0000.0101.4001

Executing POST w/%o0 = 0000.0000.0101.4001
0:0>
0:0>@(#) Sun Fire[TM] V480/V490 POST 4.18.2 2005/06/30 08:13
       /export/delivery/delivery/4.18/4.18.2/post4.18.0/Camelot/cstone/integrated  (root)  
0:0>Copyright 2005 Sun Microsystems, Inc. All rights reserved
  SUN PROPRIETARY/CONFIDENTIAL.
  Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>diag-switch? configuration variable set TRUE.
0:0>Diag level set to MAX.
0:0>MFG scrpt mode set NORM
0:0>I/O port set to serial TTYA.
0:0>
0:0>Start selftest...
0:0>Parking core 1
2:0>Parking core 1
0:0>CPUs present in system: 0:0 2:0
0:0>Test CPU(s).....
0:0>Init CPU
0:0>    UltraSparc_IV Version 3.1
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>Probe Ecache
0:0>    Size = 00000000.00800000...
0:0>Ecache Data Bitwalk
0:0>Ecache Address Bitwalk
0:0>Scrub and Setup Ecache
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
2:0>Init CPU
2:0>    UltraSparc_IV Version 3.1
2:0>DMMU Registers Access
2:0>DMMU TLB DATA RAM Access
2:0>DMMU TLB TAGS Access
2:0>IMMU Registers Access
2:0>IMMU TLB DATA RAM Access
2:0>IMMU TLB TAGS Access
2:0>Probe Ecache
2:0>    Size = 00000000.00800000...
2:0>Ecache Data Bitwalk
2:0>Ecache Address Bitwalk
2:0>Scrub and Setup Ecache
2:0>Setup and Enable DMMU
2:0>Setup DMMU Miss Handler
2:0>Test and Init Temp Mailbox
0:0>Init Scan/I2C.....
0:0>Initializing Scan Database
0:0>Mask DAR errors off
0:0>Init CDX DTL
0:0>Init DAR DTL
0:0>Enable Partial DAR error
0:0>Init DCS DTL
0:0>Init I2C
0:0>Unquiesce Safari
0:0>Margin all voltages to nominal
0:0>Scan ring integrity
0:0>
0:0>INFO: H/W under test = CPU Board Slot B (Cheetah 1, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
0:0>
0:0>INFO: H/W under test = CPU Board Slot B (Cheetah 3, SRAMs) Scan Ring NOT Present or Shut OFF
0:0>Set Trip Temp CPU 0 to 110C
0:0>Set Trip Temp CPU 2 to 110C
0:0>NULL NULL  16 1:82:03 GMT 0
0:0>Safari quick check
0:0>     to IO-bridge_0
0:0>     to IO-bridge_1
0:0>Safari full  check
0:0>     to IO-bridge_0
0:0>     to IO-bridge_1
0:0>Disable CPU 0 error checking
0:0>Disable CPU 2 error checking
0:0>Basic Memory Test.....
0:0>Probe and Setup Memory
0:0>INFO:         1024MB Bank 0
0:0>INFO:       No memory detected in Bank 1
0:0>INFO:         1024MB Bank 2
0:0>INFO:       No memory detected in Bank 3
0:0>
0:0>Data Bitwalk on Master
0:0>    Test Bank 0.
0:0>    Test Bank 2.
0:0>Address Bitwalk on Master
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 0: 00000000.00000000 to 00000000.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 2: 00000002.00000000 to 00000002.40000000.
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is ddb2.
0:0>The Memory's Content Size value is ac9ec.
0:0>
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = Incorrect checksum detected!!
        Expected: ddb2
        Observed:    c
0:0>END_ERROR

0:0>Verifying checksum on PROM.
0:0>The PROM's CHECKSUM value is ddb2.
0:0>The PROM's Content Size value is ac9ec.
0:0>Calculating Checksum on PROM's Contents.  This may take a little while.  Please wait...
0:0>
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = Incorrect checksum detected!!
        Expected: ddb2
        Observed:    c
0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG =
         *** Test Failed!! ***

0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = ERROR:        Memory error on master CPU, rolling over to new master.
0:0>END_ERROR
             :0>Soft Reset.
2:0>
2:0>Start selftest...
2:0>Parking core 1
0:0>Parking core 1
2:0>CPUs present in system: 0:0 2:0
2:0>Test CPU(s).....
2:0>Init CPU
2:0>    UltraSparc_IV Version 3.1
2:0>DMMU Registers Access
2:0>DMMU TLB DATA RAM Access
2:0>DMMU TLB TAGS Access
2:0>IMMU Registers Access
2:0>IMMU TLB DATA RAM Access
2:0>IMMU TLB TAGS Access
2:0>Probe Ecache
2:0>    Size = 00000000.00800000...
2:0>Ecache Data Bitwalk
2:0>Ecache Address Bitwalk
2:0>Scrub and Setup Ecache
2:0>Setup and Enable DMMU
2:0>Setup DMMU Miss Handler
2:0>Test and Init Temp Mailbox
0:0>Init CPU
0:0>    UltraSparc_IV Version 3.1
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>Probe Ecache
0:0>    Size = 00000000.00800000...
0:0>Ecache Data Bitwalk
0:0>Ecache Address Bitwalk
0:0>Scrub and Setup Ecache
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
2:0>Init Scan/I2C.....
2:0>Initializing Scan Database
2:0>Mask DAR errors off
2:0>Init CDX DTL
2:0>Init DAR DTL
2:0>Enable Partial DAR error
2:0>Init DCS DTL
2:0>Init I2C
2:0>Unquiesce Safari
2:0>Margin all voltages to nominal
2:0>Scan ring integrity
2:0>
2:0>INFO: H/W under test = CPU Board Slot B (Cheetah 1, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
2:0>
2:0>INFO: H/W under test = CPU Board Slot B (Cheetah 3, SRAMs) Scan Ring NOT Present or Shut OFF
2:0>Set Trip Temp CPU 0 to 110C
2:0>Set Trip Temp CPU 2 to 110C
2:0>NULL NULL  16 1:83:04 GMT 0
2:0>Safari quick check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
2:0>Safari full  check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
2:0>Disable CPU 0 error checking
2:0>Disable CPU 2 error checking
2:0>Basic Memory Test.....
2:0>Probe and Setup Memory
2:0>
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = No Memory Detected
2:0>END_ERROR

2:0>
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG =
         *** Test Failed!! ***

2:0>END_ERROR

2:0>
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = ERROR:        Memory error on master CPU, rolling over to new master.
2:0>END_ERROR

0:0>Soft Reset.
两个cpu板，同样错误，内存也换过了

dotallstar

换CPU板吧

东方蜘蛛

怀疑没插好

RMB

似乎每组内存都有问题，才会如此报错。最好找块好板子（带内存的）测试一下，新换的内存能保证没有问题吗？

fjmydfh

内存，我在880上试过，最大自测过的。cpu板我有两块其中一块是借的，在人家机上没问题。

sun-start

cpu0  cpu2内存，cpu板，cpu背板插槽，一个一个试

RMB

那就照蜘蛛所言，重新插插内存什么。还有这类服务器背板很不好使，注意上板子力度均匀

fjmydfh

cpu板和内存，我已经重插过N次了，A，B位置问题一样。会不会是中心板的问题？？？

goldfishway

880的内存不一定490 890 能用

501-5030 501-7385 501-6109 501-7386 这个能在480 490 上通用

256M的 501-5401 不能在490上用
1G的    501-5031 以也不能