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Hardware Power On
@(#)OBP 4.18.8 2006/01/19 11:19 Sun Fire 8XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 CMP1 CMP2 CMP3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing MDR via JTAG...Done
Enabling DAR error circuitry...Done
Probing Motherboard....part# 501-7199-01 serial# 008509
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Board......part# 501-7225-01 serial# 000315
Probing System RSC.....part# 501-7314-01 serial# HG05XN
Probing PwrDistBoard...part# 375-3405-01 serial# 015814
Probing PowerSupply0...part# 300-1622-05 serial# 044238
Probing PowerSupply1...part# 300-1622-05 serial# 044240
Probing PowerSupply2...part# 300-1622-05 serial# 044241
Probing GPTwo Slot A...part# 501-7481-01 serial# 004877
CPU rated speed 1500MHz; ECache 32MB 3.3ns
Probing GPTwo Slot B...part# 501-7481-01 serial# 003229
CPU rated speed 1500MHz; ECache 32MB 3.3ns
Probing GPTwo Slot C...No module detected
Probing GPTwo Slot D...No module detected
Desired Safari Bus speed 150MHz, selecting 150MHz
Setting system bus speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP 4.18.8 2006/01/19 11:19 Sun Fire 8XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 CMP1 CMP2 CMP3*
Configuring CPUs..........
..CMP0.0 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP0.1 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP1.0 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP1.1 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP2.0 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP2.1 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP3.0 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct
..CMP3.1 Speed 1500MHz Ecache 32MB 3.3ns mode=5-5-6(2)4 direct Done
<*>
CPU Configuration Reset
@(#)OBP 4.18.8 2006/01/19 11:19 Sun Fire 8XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CMP0 UltraSPARC IV+ (v2.2) 10:1 1500MHz 32MB 5:1 ECache
Online: CMP1 UltraSPARC IV+ (v2.2) 10:1 1500MHz 32MB 5:1 ECache
Online: CMP2 UltraSPARC IV+ (v2.2) 10:1 1500MHz 32MB 5:1 ECache
Online: *CMP3 UltraSPARC IV+ (v2.2) 10:1 1500MHz 32MB 5:1 ECache
Executing POST w/%o0 = 0000.1000.0101.4043
0:0>
0:0>@(#) Sun Fire[TM] V880/V890 POST 4.18.8 2006/01/19 11:29
/export/delivery/delivery/4.18/4.18.8/post4.18.0/Camelot/daktari/integrated (root)
0:0>Copyright ?2006 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>diag-switch? configuration variable set TRUE.
0:0>Keyswitch in DIAGNOSTIC POSITION.
0:0>Diag level set to MAX.
0:0>Verbosity level set to MAX.
0:0>MFG scrpt mode set NORM
0:0>I/O port set to serial TTYA.
0:0>
0:0>Start selftest...
0:0>Parking core 1
1:0>Parking core 1
2:0>Parking core 1
3:0>Parking core 1
0:0>CPUs present in system: 0:0 1:0 2:0 3:0
0:0>Test CPU(s).....
0:0>Init CPU
0:0> UltraSparc_IV+ Version 2.2
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>L2 Cache Enable
0:0>L2 cache Data Bitwalk
0:0>L2 cache Address Bitwalk
0:0>Probe L3 cache
0:0> Size = 00000000.02000000...
0:0>L3 cache Data Bitwalk
0:0>L3 cache Address Bitwalk
0:0>Scrub and Setup L3 cache
0:0>Parking core 1
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
1:0>Init CPU
2:0>Init CPU
3:0>Init CPU
1:0> UltraSparc_IV+ Version 2.2
2:0> UltraSparc_IV+ Version 2.2
3:0> UltraSparc_IV+ Version 2.2
1:0>DMMU Registers Access
2:0>DMMU Registers Access
3:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
2:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
2:0>DMMU TLB TAGS Access
3:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
2:0>IMMU Registers Access
3:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
2:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
2:0>IMMU TLB TAGS Access
3:0>IMMU TLB TAGS Access
1:0>L2 Cache Enable
2:0>L2 Cache Enable
3:0>L2 Cache Enable
1:0>L2 cache Data Bitwalk
2:0>L2 cache Data Bitwalk
3:0>L2 cache Data Bitwalk
1:0>L2 cache Address Bitwalk
2:0>L2 cache Address Bitwalk
3:0>L2 cache Address Bitwalk
1:0>Probe L3 cache
1:0> Size = 00000000.02000000...
2:0>Probe L3 cache
2:0> Size = 00000000.02000000...
3:0>Probe L3 cache
3:0> Size = 00000000.02000000...
1:0>L3 cache Data Bitwalk
2:0>L3 cache Data Bitwalk
3:0>L3 cache Data Bitwalk
1:0>L3 cache Address Bitwalk
2:0>L3 cache Address Bitwalk
3:0>L3 cache Address Bitwalk
1:0>Scrub and Setup L3 cache
2:0>Scrub and Setup L3 cache
3:0>Scrub and Setup L3 cache
1:0>Parking core 1
2:0>Parking core 1
3:0>Parking core 1
1:0>Setup and Enable DMMU
2:0>Setup and Enable DMMU
3:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
2:0>Setup DMMU Miss Handler
3:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
2:0>Test and Init Temp Mailbox
3:0>Test and Init Temp Mailbox
0:0>Init Scan/I2C.....
0:0>Initializing Scan Database
0:0>Mask DAR errors off
0:0>Init MDR DTL
0:0>Init DAR DTL
0:0>Enable Partial DAR error
0:0>Init DCS DTL
0:0>Init I2C
0:0>Unquiesce Safari
0:0>Margin all voltages to nominal
0:0>Scan ring integrity
0:0>
0:0>INFO: H/W under test = CPU Board Slot C (CPU 4, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
0:0>
0:0>INFO: H/W under test = CPU Board Slot D (CPU 5, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
0:0>
0:0>INFO: H/W under test = CPU Board Slot C (CPU 6, SRAMs) Scan Ring NOT Present or Shut OFF
0:0>
0:0>INFO: H/W under test = CPU Board Slot D (CPU 7, SRAMs) Scan Ring NOT Present or Shut OFF
0:0>Set Trip Temp CPU 0 to 110C
0:0>Set Trip Temp CPU 1 to 110C
0:0>Set Trip Temp CPU 2 to 110C
0:0>Set Trip Temp CPU 3 to 110C
0:0>SUN DEC 19 23:50:46 GMT 10
0:0>Safari quick check
0:0> to IO-bridge_0
0:0> to IO-bridge_1
0:0>Safari full check
0:0> to IO-bridge_0
0:0> to IO-bridge_1
0:0>Disable CPU 0 error checking
0:0>Disable CPU 1 error checking
0:0>Disable CPU 2 error checking
0:0>Disable CPU 3 error checking
0:0>Basic Memory Test.....
0:0>Probe and Setup Memory
0:0>INFO: 1024MB Bank 0
0:0>INFO: 1024MB Bank 1
0:0>INFO: 1024MB Bank 2
0:0>INFO: 1024MB Bank 3
0:0>
0:0>Data Bitwalk on Master
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Address Bitwalk on Master
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 0: 00000000.00000000 to 00000000.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 1: 00000001.00000000 to 00000001.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 2: 00000002.00000000 to 00000002.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 3: 00000003.00000000 to 00000003.40000000.
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is a677.
0:0>The Memory's Content Size value is add66.
0:0>Success... Checksum on Memory Validated.
1:0>Safari quick check
1:0> to IO-bridge_0
1:0> to IO-bridge_1
1:0>Safari full check
1:0> to IO-bridge_0
1:0> to IO-bridge_1
2:0>Safari quick check
2:0> to IO-bridge_0
2:0> to IO-bridge_1
2:0>Safari full check
2:0> to IO-bridge_0
2:0> to IO-bridge_1
3:0>Safari quick check
3:0> to IO-bridge_0
3:0> to IO-bridge_1
3:0>Safari full check
3:0> to IO-bridge_0
3:0> to IO-bridge_1
1:0>Probe and Setup Memory
2:0>Probe and Setup Memory
3:0>Probe and Setup Memory
1:0>INFO: 1024MB Bank 0
1:0>INFO: 1024MB Bank 1
1:0>INFO: 1024MB Bank 2
1:0>INFO: 1024MB Bank 3
1:0>
2:0>INFO: 1024MB Bank 0
2:0>INFO: 1024MB Bank 1
2:0>INFO: 1024MB Bank 2
2:0>INFO: 1024MB Bank 3
2:0>
3:0>INFO: 1024MB Bank 0
3:0>INFO: 1024MB Bank 1
3:0>INFO: 1024MB Bank 2
3:0>INFO: 1024MB Bank 3
3:0>
1:0>Set Mailbox
2:0>Set Mailbox
3:0>Set Mailbox
0:0>Data Bitwalk on Slave 1
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Data Bitwalk on Slave 2
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Data Bitwalk on Slave 3
0:0> Test Bank 0.
0:0> Test Bank 1.
0:0> Test Bank 2.
0:0> Test Bank 3.
0:0>Address Bitwalk on Slave 1
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 0: 00000010.00000000 to 00000010.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 1: 00000011.00000000 to 00000011.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 2: 00000012.00000000 to 00000012.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 3: 00000013.00000000 to 00000013.40000000.
0:0>Address Bitwalk on Slave 2
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 0: 00000020.00000000 to 00000020.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 1: 00000021.00000000 to 00000021.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 2: 00000022.00000000 to 00000022.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 3: 00000023.00000000 to 00000023.40000000.
0:0>Address Bitwalk on Slave 3
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 0: 00000030.00000000 to 00000030.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 1: 00000031.00000000 to 00000031.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 2: 00000032.00000000 to 00000032.40000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 3: 00000033.00000000 to 00000033.40000000.
1:0>Setup Final DMMU Entries
2:0>Setup Final DMMU Entries
3:0>Setup Final DMMU Entries
1:0>Map Slave POST to master memory
2:0>Map Slave POST to master memory
3:0>I-Cache Branch Predict Array Test
0:0>I-Cache Branch Predict Array Test
1:0>I-Cache Branch Target Buffer Data Test
2:0>I-Cache Branch Target Buffer Data Test
3:0>I-Cache Branch Target Buffer Data Test
0:0>I-Cache Branch Target Buffer Data Test
1:0>Instruction Cache Snoop Tag Field
2:0>Instruction Cache Snoop Tag Field
3:0>Instruction Cache Snoop Tag Field
0:0>Instruction Cache Snoop Tag Field
1:0>Instruction Prefetch Buffer Data Test
2:0>Instruction Prefetch Buffer Data Test
3:0>Instruction Prefetch Buffer Data Test
0:0>Instruction Prefetch Buffer Data Test
1:0>Instruction Prefetch Buffer Tag Test
2:0>Instruction Prefetch Buffer Tag Test
3:0>Instruction Prefetch Buffer Tag Test
0:0>Instruction Prefetch Buffer Tag Test
1:0>Flush D/W caches
2:0>Flush D/W caches
3:0>Flush D/W caches
0:0>Flush D/W caches
1:0>Data Cache RAM
2:0>Data Cache RAM
3:0>Data Cache RAM
0:0>Data Cache RAM
1:0>Data Cache Tags
2:0>Data Cache Tags
3:0>Data Cache Tags
0:0>Data Cache Tags
1:0>Data Micro Tags
2:0>Data Micro Tags
3:0>Data Micro Tags
0:0>Data Micro Tags
1:0>D-Cache SnoopTags Test
2:0>D-Cache SnoopTags Test
3:0>D-Cache SnoopTags Test
0:0>D-Cache SnoopTags Test
1:0>WCache RAM
2:0>WCache RAM
3:0>WCache RAM
0:0>WCache RAM
1:0>WCache Tags
2:0>WCache Tags
3:0>WCache Tags
0:0>WCache Tags
1:0>W-Cache Valid bit Test
2:0>W-Cache Valid bit Test
3:0>W-Cache Valid bit Test
0:0>W-Cache Valid bit Test
1:0>W-Cache Bank valid bit Test
2:0>W-Cache Bank valid bit Test
3:0>W-Cache Bank valid bit Test
0:0>W-Cache Bank valid bit Test
1:0>W-Cache SnoopTAGS Test
2:0>W-Cache SnoopTAGS Test
3:0>W-Cache SnoopTAGS Test
0:0>W-Cache SnoopTAGS Test
1:0>Prefetch Cache RAM
2:0>Prefetch Cache RAM
3:0>Prefetch Cache RAM
0:0>Prefetch Cache RAM
1:0>Prefetch Cache Tags
2:0>Prefetch Cache Tags
3:0>Prefetch Cache Tags
0:0>Prefetch Cache Tags
1:0>P-Cache SnoopTags Test
2:0>P-Cache SnoopTags Test
3:0>P-Cache SnoopTags Test
0:0>P-Cache SnoopTags Test
1:0>P-Cache Status Data Test
2:0>P-Cache Status Data Test
3:0>P-Cache Status Data Test
0:0>P-Cache Status Data Test
1:0>Branch Prediction Initialization
2:0>Branch Prediction Initialization
3:0>Branch Prediction Initialization
0:0>Branch Prediction Initialization
1:0>Scrub Memory
2:0>Scrub Memory
3:0>Scrub Memory
0:0>Memory Block.....
0:0>Scrub Memory
1:0>Print Mem Config
1:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1:0>Memory in non-interleave config:
1:0> Bank 0 1024MB : 00000010.00000000 -> 00000010.40000000.
1:0> Bank 1 1024MB : 00000011.00000000 -> 00000011.40000000.
1:0> Bank 2 1024MB : 00000012.00000000 -> 00000012.40000000.
1:0> Bank 3 1024MB : 00000013.00000000 -> 00000013.40000000.
2:0>Print Mem Config
2:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:0>Memory in non-interleave config:
2:0> Bank 0 1024MB : 00000020.00000000 -> 00000020.40000000.
2:0> Bank 1 1024MB : 00000021.00000000 -> 00000021.40000000.
2:0> Bank 2 1024MB : 00000022.00000000 -> 00000022.40000000.
2:0> Bank 3 1024MB : 00000023.00000000 -> 00000023.40000000.
3:0>Print Mem Config
3:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3:0>Memory in non-interleave config:
3:0> Bank 0 1024MB : 00000030.00000000 -> 00000030.40000000.
3:0> Bank 1 1024MB : 00000031.00000000 -> 00000031.40000000.
3:0> Bank 2 1024MB : 00000032.00000000 -> 00000032.40000000.
3:0> Bank 3 1024MB : 00000033.00000000 -> 00000033.40000000.
1:0>Quick Block Mem Test
2:0>Quick Block Mem Test
1:0>Quick Test 67108864 bytes at 00000010.00000000
2:0>Quick Test 67108864 bytes at 00000020.00000000
3:0>Quick Block Mem Test
0:0>Print Mem Config
0:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:0>Memory in non-interleave config:
0:0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.
0:0> Bank 1 1024MB : 00000001.00000000 -> 00000001.40000000.
0:0> Bank 2 1024MB : 00000002.00000000 -> 00000002.40000000.
0:0> Bank 3 1024MB : 00000003.00000000 -> 00000003.40000000.
3:0>Quick Test 67108864 bytes at 00000030.00000000
0:0>Quick Block Mem Test
0:0>Quick Test 67108864 bytes at 00000000.00600000
0:0>10% Done...
0:0>32% Done...
0:0>54% Done...
0:0>76% Done...
0:0>98% Done...
1:0>Flush Caches
2:0>Flush Caches
3:0>Flush Caches
0:0>Flush Caches
1:0>Get code in ecache.
2:0>Get code in ecache.
3:0>Get code in ecache.
0:0>Get code in ecache.
0:0>IO-Bridge Tests.....
0:0>IO-Bridge unit 0 init test
0:0>IO-Bridge unit 1 init test
1:0>Enabling core 1
2:0>Enabling core 1
3:0>Enabling core 1
0:0>Enabling core 1
0:1>Init CPU
0:1> UltraSparc_IV+ Version 2.2
1:1>Init CPU
2:1>Init CPU
3:1>Init CPU
1:1> UltraSparc_IV+ Version 2.2
2:1> UltraSparc_IV+ Version 2.2
3:1> UltraSparc_IV+ Version 2.2
0:1>DMMU Registers Access
1:1>DMMU Registers Access
2:1>DMMU Registers Access
3:1>DMMU Registers Access
0:1>DMMU TLB DATA RAM Access
1:1>DMMU TLB DATA RAM Access
2:1>DMMU TLB DATA RAM Access
3:1>DMMU TLB DATA RAM Access
0:1>DMMU TLB TAGS Access
1:1>DMMU TLB TAGS Access
2:1>DMMU TLB TAGS Access
3:1>DMMU TLB TAGS Access
0:1>IMMU Registers Access
1:1>IMMU Registers Access
2:1>IMMU Registers Access
3:1>IMMU Registers Access
0:1>IMMU TLB DATA RAM Access
1:1>IMMU TLB DATA RAM Access
2:1>IMMU TLB DATA RAM Access
3:1>IMMU TLB DATA RAM Access
0:1>IMMU TLB TAGS Access
1:1>IMMU TLB TAGS Access
2:1>IMMU TLB TAGS Access
3:1>IMMU TLB TAGS Access
0:1>Setup and Enable DMMU
1:1>Setup and Enable DMMU
2:1>Setup and Enable DMMU
3:1>Setup and Enable DMMU
0:1>Setup DMMU Miss Handler
1:1>Setup DMMU Miss Handler
2:1>Setup DMMU Miss Handler
3:1>Setup DMMU Miss Handler
0:1>Test and Init Temp Mailbox
3:1>8k DMMU TLB 1 Data
0:1>8k DMMU TLB 0 Tags
1:1>8k DMMU TLB 0 Tags
2:1>8k DMMU TLB 0 Tags
3:1>8k DMMU TLB 0 Tags
0:1>8k DMMU TLB 1 Tags
1:1>8k DMMU TLB 1 Tags
2:1>8k DMMU TLB 1 Tags
3:1>8k DMMU TLB 1 Tags
0:1>8k IMMU TLB Data
1:1>8k IMMU TLB Data
2:1>8k IMMU TLB Data
3:1>8k IMMU TLB Data
0:1>8k IMMU TLB Tags
1:1>8k IMMU TLB Tags
2:1>8k IMMU TLB Tags
3:1>8k IMMU TLB Tags
0:1>Instruction Cache Tag RAM
1:1>Instruction Cache Tag RAM
2:1>Instruction Cache Tag RAM
3:1>Instruction Cache Tag RAM
0:1>Instruction Cache RAM
1:1>Instruction Cache RAM
2:1>Instruction Cache RAM
3:1>Instruction Cache RAM
0:1>I-Cache Valid/Predict TAGS Test
1:1>I-Cache Valid/Predict TAGS Test
2:1>I-Cache Valid/Predict TAGS Test
3:1>I-Cache Valid/Predict TAGS Test
0:1>I-Cache Branch Predict Array Test
1:1>I-Cache Branch Predict Array Test
2:1>I-Cache Branch Predict Array Test
3:1>I-Cache Branch Predict Array Test
0:1>I-Cache Branch Target Buffer Data Test
1:1>I-Cache Branch Target Buffer Data Test
1:1>Prefetch Cache RAM
2:1>Prefetch Cache RAM
0:1>Prefetch Cache Tags
1:1>Prefetch Cache Tags
3:1>Prefetch Cache RAM
2:1>Prefetch Cache Tags
3:1>Branch Prediction Initialization
0:0>Waiting for slave CPU=0:1, timeout in 67 seconds...
0:1>Print Mem Config
0:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1:1>Print Mem Config
1:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:1>Print Mem Config
2:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3:1>Print Mem Config
3:1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:1>Flush Caches
1:1>Flush Caches
2:1>Flush Caches
3:1>Flush Caches
1:1>FSR Read/Write
0:1>FPU Branch Instructions
2:1>FSR Read/Write
3:1>FSR Read/Write
1:1>FPU Branch Instructions
0:1>FPU Functional Test
2:1>FPU Branch Instructions
3:1>FPU Branch Instructions
1:1>FPU Functional Test
0:1>FPU BLOCK REG TEST
2:1>FPU Functional Test
3:1>FPU Functional Test
0:1>NOTE: FPU REG BLK TEST NOT EXECUTED FOR PANTHER CPUs.
1:1>FPU BLOCK REG TEST
1:1>NOTE: FPU REG BLK TEST NOT EXECUTED FOR PANTHER CPUs.
2:1>FPU BLOCK REG TEST
3:1>FPU BLOCK REG TEST
2:1>NOTE: FPU REG BLK TEST NOT EXECUTED FOR PANTHER CPUs.
3:1>NOTE: FPU REG BLK TEST NOT EXECUTED FOR PANTHER CPUs.
0:0>IO-Bridge unit 0 reg test
0:0>IO-Bridge unit 0 mem test
0:0>IO-Bridge unit 0 PCI DMA A test
0:0>IO-Bridge unit 0 PCI DMA B test
0:0>IO-Bridge unit 0 PCI merg test
0:0>IO-Bridge unit 0 PCI iommu test
0:0>IO-Bridge unit 0 PCI stc test
0:0>IO-Bridge unit 0 interrupt test
0:0>IO-Bridge unit 1 reg test
0:0>IO-Bridge unit 1 mem test
0:0>IO-Bridge unit 1 PCI DMA C test
1:0>Watchdog Reset!
1:0>
1:0>ERROR: TEST = Power on Reset Initialization
1:0>H/W under test = CPU0 Basic, Motherboard/Centerplane
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = Watchdog timeout, Master CPU Failure on 0:0, rollover to 1:0.
1:0>END_ERROR
1:0>INFO: Reset Module with CPUs 0 2, both have been offlined.
主机反复重启，主板（肯定是好的）换过，但问题仍然存在。请求各位帮忙分析一下。多谢了..... |
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发表于 2010-12-20 10:03
