u-boot解析注释（EN）

osama123

    下载了u-boot，看了看里面的代码，并加入了一些注释，由于刚开始学arm以及汇编，因此加入了一些对汇编的注释：
    包含如下文件：
    1. board/lowlevel_init.S
    2. cpu/arm920t/start.S
    下面是start.S的内容：
/*
*  armboot - Startup Code for ARM920 CPU-core
*
*  Copyright (c) 2001    Marius Gr鰃er
*  Copyright (c) 2002    Alex Z黳ke
*  Copyright (c) 2002    Gary Jennejohn
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include
#include
#include
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start:    b       start_code
    ldr    pc, _undefined_instruction
    ldr    pc, _software_interrupt
    ldr    pc, _prefetch_abort
    ldr    pc, _data_abort
    ldr    pc, _not_used
    ldr    pc, _irq
    ldr    pc, _fiq
_undefined_instruction:    .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:        .word not_used
_irq:            .word irq
_fiq:            .word fiq
    .balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
_TEXT_BASE:
    .word    TEXT_BASE
.globl _armboot_start
_armboot_start:
    .word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
    .word __bss_start
.globl _bss_end
_bss_end:
    .word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
    .word    0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
    .word 0x0badc0de
#endif
/*
* the actual start code
*/
start_code:
    /*
     * set the cpu to SVC32 mode
     */
    mrs    r0,cpsr /*get the cpsr to r0*/
    bic    r0,r0,#0x1f /*bit clear the mode bits to 0 */
    orr    r0,r0,#0xd3 /*set the mode to the svc32 mode, and disable irq and firq at the same time*/
    msr    cpsr,r0 /*set the cpsr*/
    bl coloured_LED_init /*call subroutine, bl is the branch with link instruction, init the led, the coloured_LED_init() is in status_led.h*/
    bl red_LED_on
#if    defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
    /*
     * relocate exception table
     */
    ldr    r0, =_start
    ldr    r1, =0x0
    mov    r2, #16
copyex:
    subs    r2, r2, #1
    ldr    r3, [r0], #4
    str    r3, [r1], #4
    bne    copyex
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
    /* turn off the watchdog */
# if defined(CONFIG_S3C2400)
#  define pWTCON        0x15300000
#  define INTMSK        0x14400008    /* Interupt-Controller base addresses */
#  define CLKDIVN    0x14800014    /* clock divisor register */
#else
#  define pWTCON        0x53000000
#  define INTMSK        0x4A000008    /* Interupt-Controller base addresses */
#  define INTSUBMSK    0x4A00001C
#  define CLKDIVN    0x4C000014    /* clock divisor register */
# endif
    ldr     r0, =pWTCON /*here, the ldr is a directive instruction, it will be divided into multiple instructions, which load the address represented by pWTCON to the r0 register*/
    mov     r1, #0x0
    str     r1, [r0] /*store 0 to the watchdog controller*/
    /*
     * mask all IRQs by setting all bits in the INTMR - default
     */
    mov    r1, #0xffffffff /*when moving imediate data into registers, the data should be the result of shifting even number of bits from a 8bit number*/
    ldr    r0, =INTMSK
    str    r1, [r0] /*disable all ints*/
# if defined(CONFIG_S3C2410)
    ldr    r1, =0x3ff
    ldr    r0, =INTSUBMSK
    str    r1, [r0]
# endif
    /* FCLK:HCLK:PCLK = 1:2:4 */
    /* default FCLK is 120 MHz ! */
    ldr    r0, =CLKDIVN /*clock division register*/
    mov    r1, #3
    str    r1, [r0]
#endif    /* CONFIG_S3C2400 || CONFIG_S3C2410 */
    /*
     * we do sys-critical inits only at reboot,
     * not when booting from ram!
     */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif
#ifdef    CONFIG_AT91RM9200
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
    /* adr put the address of _start into r0, ldr put the content at _TEXT_BASE into r1, that is the
     predetermined value "TEXT_BASE"*/
relocate:                /* relocate U-Boot to RAM        */
    adr    r0, _start        /* r0
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include
#include
/* some parameters for the board */
/*
*
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
*
* Copyright (C) 2002 Samsung Electronics SW.LEE  
*
*/
#define BWSCON    0x48000000
/* BWSCON */
#define DW8             (0x0)
#define DW16             (0x1)
#define DW32             (0x2)
#define WAIT             (0x1<<2)
#define UBLB             (0x1<<3)
#define B1_BWSCON          (DW32)
#define B2_BWSCON          (DW16)
#define B3_BWSCON          (DW16 + WAIT + UBLB)
#define B4_BWSCON          (DW16)
#define B5_BWSCON          (DW16)
#define B6_BWSCON          (DW32)
#define B7_BWSCON          (DW32)
/* BANK0CON */
#define B0_Tacs             0x0    /*  0clk */
#define B0_Tcos             0x0    /*  0clk */
#define B0_Tacc             0x7    /* 14clk */
#define B0_Tcoh             0x0    /*  0clk */
#define B0_Tah             0x0    /*  0clk */
#define B0_Tacp             0x0
#define B0_PMC             0x0    /* normal */
/* BANK1CON */
#define B1_Tacs             0x0    /*  0clk */
#define B1_Tcos             0x0    /*  0clk */
#define B1_Tacc             0x7    /* 14clk */
#define B1_Tcoh             0x0    /*  0clk */
#define B1_Tah             0x0    /*  0clk */
#define B1_Tacp             0x0
#define B1_PMC             0x0
#define B2_Tacs             0x0
#define B2_Tcos             0x0
#define B2_Tacc             0x7
#define B2_Tcoh             0x0
#define B2_Tah             0x0
#define B2_Tacp             0x0
#define B2_PMC             0x0
#define B3_Tacs             0x0    /*  0clk */
#define B3_Tcos             0x3    /*  4clk */
#define B3_Tacc             0x7    /* 14clk */
#define B3_Tcoh             0x1    /*  1clk */
#define B3_Tah             0x0    /*  0clk */
#define B3_Tacp             0x3     /*  6clk */
#define B3_PMC             0x0    /* normal */
#define B4_Tacs             0x0    /*  0clk */
#define B4_Tcos             0x0    /*  0clk */
#define B4_Tacc             0x7    /* 14clk */
#define B4_Tcoh             0x0    /*  0clk */
#define B4_Tah             0x0    /*  0clk */
#define B4_Tacp             0x0
#define B4_PMC             0x0    /* normal */
#define B5_Tacs             0x0    /*  0clk */
#define B5_Tcos             0x0    /*  0clk */
#define B5_Tacc             0x7    /* 14clk */
#define B5_Tcoh             0x0    /*  0clk */
#define B5_Tah             0x0    /*  0clk */
#define B5_Tacp             0x0
#define B5_PMC             0x0    /* normal */
#define B6_MT             0x3    /* SDRAM */
#define B6_Trcd              0x1
#define B6_SCAN             0x1    /* 9bit */
#define B7_MT             0x3    /* SDRAM */
#define B7_Trcd             0x1    /* 3clk */
#define B7_SCAN             0x1    /* 9bit */
/* REFRESH parameter */
#define REFEN             0x1    /* Refresh enable */
#define TREFMD             0x0    /* CBR(CAS before RAS)/Auto refresh */
#define Trp             0x0    /* 2clk */
#define Trc             0x3    /* 7clk */
#define Tchr             0x2    /* 3clk */
#define REFCNT             1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE:
    .word    TEXT_BASE
.globl lowlevel_init
lowlevel_init:
    /* memory control configuration */
    /* make r0 relative the current location so that it */
    /* reads SMRDATA out of FLASH rather than memory ! */
    ldr     r0, =SMRDATA /* this ldr is a directive, not an arm instruction, it just takes the value of SMRDATA into r0*/
    ldr    r1, _TEXT_BASE /* this ldr is a formal arm instruction, it takes the content at the address _TEXT_BASE into r1*/
    sub    r0, r0, r1
    ldr    r1, =BWSCON    /* Bus Width Status Controller */ /*this is a directive, it just fills r1 with BWSCON, which is the address of bus width status controller*/
    add     r2, r0, #13*4 /*r2 points to the end of the SMRDATA section*/
0:
/*copy SMRDATA contents into BWSCON*/
    ldr     r3, [r0], #4
    str     r3, [r1], #4
    cmp     r2, r0
    bne     0b
    /* everything is fine now */
    mov    pc, lr
    /*as we store some imediate numbers into registers, so the compiler may
     create some literial area to store imediate numnber, in order to locate
     them in a position that we can reach that is (+/-4k from the pc), we manually
     create a literal pool using the directive ".ltorg"*/
    .ltorg
/* the literal pools origin */
SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .word 0x32
    .word 0x30
    .word 0x30
    从start.S开始，执行start_code处的指令，
    1。依次设置为SVC32 mode,
    2。LED init, 就我目前观察，针对s3c2410/smdk2410的板子，其coloured_LED_init的代码是空的，它是__coloured_LED_init函数的alias(使用了GNUC的__attribute__来设置函数间的alias关系)。
    3。关闭watchdog
    4。关中断,INTMASK和SUBINTMASK
    5。设置fclk/hclk/pclk的比例
    6。调用cpu_init_crit代码段
    7。relocate代码段到TEXT_BASE
    8。stack_setup
    9。clear_bss，对BSS段清零
    10。启动start_armboot。
    上面的6，调用cpu_init_crit代码段完成的工作如下:
    主要是memory controll 的配置。通过向BWSCON写入相应配置数据，具体的配置数据在SMRDATA处存储。
    注意只有在lowlevel_init对存储器配置后，才可能将代码relocate到ram中。
   
    基于对上述代码的分析，可以推出，启动初期的内存布局：
    从低地址到高地址：
    stack,
    abort_stack(12bytes),
    IRQ stack( 包括irq,fiq的stack)
    bdinfor
    malloc area
    text
    bss
    此外，start.S中还包含了interrupt和exception的处理代码，有待进一步分析。start_armboot的代码也有待进一步分析。
   
               
               
               

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