一个Branch Delay Slot的问题

prolj

1，分支预测错误的恢复的确由硬件管理
2，我在看See MIPS Run，经常会有jal后面跟一条别的指令用于填充延时槽，流水线对于程序员不是完全不可见的
3，X86流水线更长，但是还有乱序执行呢。Intel 64 and IA-32 Architectures Optimization Reference Manual我还没看呢，这个...不清楚，也许我做到这一块就明白了

Wind-Son

gcc针对MIPS自动将分支指令扩展为分支+NOP指令
这是google的：
http://gcc.gnu.org/ml/gcc/2008-01/msg00577.html

Boris Boesler <baembel@gmx.de> writes:
>   I have to insert NOP-instructions into the insn-stream in my back-
> end. I do this with something ala emit_insn_after(gen_nop, xyz). This  
> works so far.
>
>   GCC leaves control-flow operations as they are, if it there are no  
> instructions which can be used to fill the branch delay slots. My  
> first idea was to convert these control-flow cf to SEQUENCE(cf) and  
> hope the GCC will invoke DBR_OUTPUT_SEQEND(), but it does not? My  
> second idea was to add these NOP-instructions: SEQUENCE(cf,  
> NOP,...,NOP). I "reused" the code in function emit_delay_sequence()  
> in reorg.c and added NOPs with:
>         XVECEXP (seq, 0, i) = emit_insn_after(tem, XVECEXP (seq, 0, i - 1));
> or
>         XVECEXP (seq, 0, i) = tem;
> But GCC will fail in both cases in final_scan_insn() or asm_noperands
> (). In both cases the CONST_INT (pattern for nop) is passed as a rtx  
> pointer.
>
> so, how do I add NOP-instructions properly?

I'm not quite sure what you're trying to do here.  Do you need to insert
nops in delay slots only, or do you need to insert nops at other places
too (such as to work around processor errata)?

If the former: you don't need to make delay-slot nops explicit in
the rtl.  Just make your branch output patterns add whatever nops
are needed.  See the MIPS port for an example.  E.g. on MIPS,
a plain "jr foo" JUMP_INSN is written as:

        jr      foo
        nop

(Specifically, MIPS uses a special '%/' asm punctuation character,
so that:

        "jr\t%0%/"

will print a nop if the rtl has no explicit delay slot.)

If you need to insert nops outside delay slots, than you should
do it after delayed-branch scheduling.  Again, MIPS has examples
of this; it calls dbr_schedule from within md_reorg.

Not sure if that's any help though, sorry...

prolj

gcc给mips插入nop，你手写汇编完全可以插入别的周期数运算指令啊，code-gen和机器相关优化分不开

prolj

开始x86了，x86的分支预测在汇编级别的确是（部分）可见的，不少优化技巧是针对这个的。
乱序并发 执行，是由退役单元决定微操作顺序的，对程序员的可见性不高啊，也可以说基本不可见。但是你写没有数据相关性的指令序列也可以改善效果，就是指令级并行。RISC机器是由指令调度决定的顺序。
llvm和lcc的x86代码生成都没有大规模的插入nop的操作，乱序并发执行对程序员可见度的确不高。

[ 本帖最后由 prolj 于 2008-7-7 23:35 编辑 ]

SuperZ

对于最简单的MIPS的CPU，延迟槽是不能忽略的，也没有分支预测，当然也没有分支预测错误的恢复机制，它总是执行的！
“实际上总是把转移目标（在这里是finished）处的第一条指令移过来，放在转移指令后面……”这句话绝对错误。这种优化只有在包含“跳转执行(branch likely)”指令的CPU上才有，也就是MIPS III。
手工汇编可以填写NOP就行了，编译器一般不会添加NOP。

prolj

多介绍一下吧

prolj

原帖由 jamesr 于 2008-7-15 14:05 发表
任何MIPS，不过复杂的还是简单的，分支延迟槽对于汇编来说是一直存在的。而且不管延迟槽有几个周期，都当作一个周期。

为什么啊？

prolj

那代码生成就好幸福了