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freescale的powerpc32位编程手册:第190页
Except for the cases described above and earlier in this section, data and control dependencies do not order
memory accesses. Examples include the following:
• If a load specifies the same memory location as a preceding store and the location is not caching
inhibited, the load may be satisfied from a store queue (a buffer into which the processor places
stored values before presenting them to the memory subsystem) and not be visible to other
processors and mechanisms. As a result, if a subsequent store depends on the value returned by the
load, the two stores need not be performed in program order with respect to other processors and
mechanisms.
按例子说,如果写向addr1,然后从addr1读,通过读出的数据决定另一个写操作,那么这两个写可能不按顺序完成.
如果两次写的地址不同,我可以理解,因为逻辑上两次写的完成不互相影响,不构成"写后写"的问题. 但是如果碰巧是"写后写"呢,文档的意思是说这里有隐患,需要的时候这里就要自己加内存屏障了吗?
上下文太长了我就不贴了, 前文大致是介绍了powerpc的乱序访存和几种sync类指令. |
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