SUN3500启动故障，请教各位高手

leon333

Hardware Power ON

@(#) Ultra Enterprise 3.2 Version 24 created 1999/12/23 17:31
CPU = 0000.0000.0000.0006
Probing keyboard Done

3,0>;
3,0>;@(#) POST 3.9.24 1999/12/23 17:35
3,1>;
3,0>;
    SelfTest Initializing (Diag Level 10, ENV 0000ff01) IMPL 0011 MASK a0
3,1>;@(#) POST 3.9.24 1999/12/23 17:35
3,0>;Board 3 CPU FPROM Test
3,1>;
    SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK a0
3,0>;Board 3 Basic CPU Test
3,0>;    Set CPU UPA Config and Init SDB Data
3,0>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,0>;Board 3 MMU Enable Test
3,0>;    DMMU Init
3,0>;    IMMU Init
3,0>;    Mapping Selftest Enabling MMUs
3,0>;Board 3 Ecache Test
3,0>;    Ecache Probe
3,0>;    Ecache Tags
3,1>;Board 3 CPU FPROM Test
3,1>;Board 3 Basic CPU Test
3,1>;    Set CPU UPA Config and Init SDB Data
3,1>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,1>;Board 3 MMU Enable Test
3,1>;    DMMU Init
3,1>;    IMMU Init
3,1>;    Mapping Selftest Enabling MMUs
3,1>;Board 3 Ecache Test
3,1>;    Ecache Probe
3,1>;    Ecache Tags
3,0>;    Ecache Quick Verify
3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3
3,0>;Component under test: Board 3 CPU 0
3,0>;    RAM compare error,
        index    1
        expected 55555555.55555555
        observed 00005555.00005555
        xor      55550000.55550000
3,1>;    Ecache Quick Verify
3,1>;    Ecache Init
3,0>;
         *** Aborting Test List due to severe error ***

3,0>;Deconfiguring CPU MID 6
3,1>;    Ecache RAM
3,1>;    Ecache Address Line
3,1>;    Configure Ecache Limit
3,1>;Ecache Size = 00800000,  Limited to 00800000
3,1>;Board 3 FPU Functional Test
3,1>;    FPU Enable
3,1>;Board 3 Board Master Select Test
3,1>;    Selecting a Board Master
3,1>;Board 3 FireHose Devices Test
3,1>;Board 3 Address Controller Test
3,1>;    AC Initialization
3,1>;    AC DTAG Init
3,1>;Board 3 Dual Tags Test
3,1>;    AC DTAG Init
3,1>;Board 3 FireHose Controller Test
3,1>;    FHC Initialization
3,1>;Board 3 JTAG Test
3,1>;    Verify System Board Scan Ring
3,1>;Board 3 Centerplane Test
3,1>;    Centerplane Join
3,1>;Setting JTAG Master
3,1>;Clear JTAG Master
3,1>;Board 3 Setup Cache Size Test
3,1>;    Setting Up Cache Size
3,1>;Board 3 System Master Select Test
3,1>;    Setting System Master
3,1>OST Master Selected (JTAG,CENTRAL)
3,1>;Board 16 Clock Board Test
3,1>;    Clock Board Initialization
3,1>;    Clock Board Temperature Check
3,1>;Board 16 Clock Board Serial Ports Test
3,1>;Board 16 NVRAM Devices Test
3,1>;    M48T59 (TOD) Init
3,1>;Board 3 System Board Probe  Test
3,1>;    Probing all CPU/Memory BDA
3,1>;    Probing System Boards
3,1>;    Probing CPU Module JTAG Rings
3,1>;Setting System Clock Frequency
3,1>;    CPU mid 6 Checked in FAILED
3,1>;    CPU Module mid 7 Checked in OK (speed code = 3)
3,1>; ******** Clock Reset - retesting
3,1>;System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400
3,1>;
3,1>;@(#) POST 3.9.24 1999/12/23 17:35
3,1>;
    SelfTest Initializing (Diag Level 40, ENV 0000ff81) IMPL 0011 MASK a0
3,1>;Board 3 CPU FPROM Test
3,1>;    CPU/Memory Board FPROM Checksum Test
3,0>;
3,0>;@(#) POST 3.9.24 1999/12/23 17:35
3,0>;
    SelfTest Initializing (Diag Level 40, ENV 0000ff81) IMPL 0011 MASK a0
3,0>;Board 3 CPU FPROM Test
3,0>;    CPU/Memory Board FPROM Checksum Test
3,1>;Board 3 Basic CPU Test
3,1>;    FPU Registers and Data Path Test
3,1>;    Instruction Cache Tag RAM Test
3,0>;Board 3 Basic CPU Test
3,0>;    FPU Registers and Data Path Test
3,1>;    Instruction Cache Instruction RAM Test
3,0>;    Instruction Cache Tag RAM Test
3,0>;    Instruction Cache Instruction RAM Test
3,1>;    Instruction Cache Next Field RAM Test
3,0>;    Instruction Cache Next Field RAM Test
3,1>;    Instruction Cache Pre-decode RAM Test
3,0>;    Instruction Cache Pre-decode RAM Test
3,1>;    Data Cache RAM Test
3,0>;    Data Cache RAM Test
3,1>;    Data Cache Tags Test
3,1>;    DMMU Registers Access Test
3,0>;    Data Cache Tags Test
3,1>;    DMMU TLB DATA RAM Access Test
3,1>;    DMMU TLB TAGS Access Test
3,1>;    IMMU Registers Access Test
3,1>;    IMMU TLB DATA RAM Access Test
3,1>;    IMMU TLB TAGS Access Test
3,1>;    Set CPU UPA Config and Init SDB Data
3,1>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,0>;    DMMU Registers Access Test
3,1>;Board 3 MMU Enable Test
3,1>;    DMMU Init
3,1>;    IMMU Init
3,1>;    Mapping Selftest Enabling MMUs
3,1>;Board 3 Ecache Test
3,1>;    Ecache Probe
3,0>;    DMMU TLB DATA RAM Access Test
3,1>;    Ecache Tags
3,0>;    DMMU TLB TAGS Access Test
3,0>;    IMMU Registers Access Test
3,0>;    IMMU TLB DATA RAM Access Test
3,0>;    IMMU TLB TAGS Access Test
3,0>;    Set CPU UPA Config and Init SDB Data
3,0>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,0>;Board 3 MMU Enable Test
3,0>;    DMMU Init
3,0>;    IMMU Init
3,0>;    Mapping Selftest Enabling MMUs
3,0>;Board 3 Ecache Test
3,0>;    Ecache Probe
3,0>;    Ecache Tags
3,1>;    Ecache Quick Verify
3,1>;    Ecache Init
3,0>;    Ecache Quick Verify
3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3
3,0>;Component under test: Board 3 CPU 0
3,0>;    RAM compare error,
        index    1
        expected 55555555.55555555
        observed 00005555.00005555
        xor      55550000.55550000
3,0>;
         *** Aborting Test List due to severe error ***

3,0>;Deconfiguring CPU MID 6
3,1>;    Ecache RAM
3,1>;    Ecache 6N RAM Pattern Test
3,1>;    Ecache Address Line
3,1>;    Configure Ecache Limit
3,1>;Ecache Size = 00800000,  Limited to 00800000
3,1>;Board 3 FPU Functional Test
3,1>;    FPU Enable
3,1>;Board 3 Board Master Select Test
3,1>;    Selecting a Board Master
3,1>;Board 3 FireHose Devices Test
3,1>;    PROM Datapath Test
3,1>;    FHC CPU SRAM Test
3,1>;Board 3 Address Controller Test
3,1>;    AC Registers Test
3,1>;    AC Initialization
3,1>;    Memory Registers  Test
3,1>;    Memory Registers Initialization Test
3,1>;    AC DTAG Init
3,1>;Board 3 Dual Tags Test
3,1>;    AC DTAG Test
3,1>;    AC DTAG Init
3,1>;Board 3 FireHose Controller Test
3,1>;    FHC Initialization
3,1>;Board 3 JTAG Test
3,1>;    Verify System Board Scan Ring
3,1>;Board 3 Centerplane Test
3,1>;    Centerplane and Arbiter Check Test
3,1>;Setting JTAG Master
3,1>;Clear JTAG Master
3,1>;    Centerplane Join
3,1>;Setting JTAG Master
3,1>;Clear JTAG Master
3,1>;Board 3 Setup Cache Size Test
3,1>;    Setting Up Cache Size
3,1>;Board 3 System Master Select Test
3,1>;    Setting System Master
3,1>OST Master Selected (JTAG,CENTRAL)
3,1>;Board 16 Clock Board Test
3,1>;    Clock Board Registers Test
3,1>;    Clock Board Initialization
3,1>;    Clock Board Temperature Check
3,1>;Board 16 Clock Board Serial Ports Test
3,1>;    85C30 Register Test
3,1>;    85C30 Serial Ports Test
3,1>;    Keyboard Loopback
3,1>;    Mouse Loopback
3,1>;    Serial Port B Loopback
3,1>;    Remote Serial Port A Loopback
3,1>;    Remote Serial Port B Loopback
3,1>;Board 16 NVRAM Devices Test
3,1>;    M48T59 (TOD) Init
3,1>;    M48T59 (TOD) Functional Part 1 Test
3,1>;    NVRAM(Non-Destructive) Test
3,1>;Board 3 System Board Probe  Test
3,1>;    Probing all CPU/Memory BDA
3,1>;    Probing System Boards
3,1>;    Probing CPU Module JTAG Rings

每次到这就无响应了，重启若干次无效，求教。

C.Arthur

你有几个CPU

paradisegame

先看~cpu板是不是没插好~如果不是，那么荣幸的告诉你可以换一个再来试试看了~！！！内存再看看！3500比较脆弱~cpu板经常容易出问题~

Philmoon

注意这一段：
3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3
3,0>;Component under test: Board 3 CPU 0
3,0>; RAM compare error,
index 1
expected 55555555.55555555
observed 00005555.00005555
xor 55550000.55550000
3,0>;
*** Aborting Test List due to severe error ***

应该是CPU有问题了。

roger0409

换一块板子试试