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有没有搞集成电路(IC Design)行业的兄弟 [复制链接]

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发表于 2004-05-18 14:57 |只看该作者 |倒序浏览
联系一下。
日子实在不好混了

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发表于 2004-05-19 15:00 |只看该作者

有没有搞集成电路(IC Design)行业的兄弟

认识几个人在SMIC
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发表于 2004-05-20 21:41 |只看该作者
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发表于 2004-05-21 10:21 |只看该作者

有没有搞集成电路(IC Design)行业的兄弟

Synopsys Shanghai R&D center is recruiting  software Engineer:


CN42-Shanghai - R&D Engineering

ReqCode: 3368
Position: Senior R&D Engineer
Location: CN42-Shanghai


Job Responsibilities:
Responsible for designing, developing, troubleshooting and debugging software programs for the leading EDA verification technology for Verilog. Will be involved in all phases of software development, including project planning, problem identification, design specifications, development, scheduling, implementation and testing. This job requires the ability to analyze and specify solutions for complex software design problems.

Job Requirements:
This position requires a MS or Ph.D. in CS/EE with 3+ years of experience in development, quality assurance and the delivery of products. You must also possess: - Excellent written and verbal communication skills - Knowledge of EDA, Solid experience on Verilog design or verification.- Experience on gate level simulation and static timing is a definite asset- Solid knowledge of C/C++ programming languages - Good debugging skills and an understanding of the software development life cycle - Self-initiative and the ability to work in a team environment - Familiarity with UNIX and Linux

eligible candidate can send your CV to csliu@synopsys.com.
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