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DV: Sr Verification Engineer
Job Responsibilities:
Apply specialist skills and knowledge in both hardware and software to perform Pre-Silicon verification tasks for complex VLSI devices
Support the development of multi abstraction/views to enable a thorough Soc verification especially in gate level
Participation in the continued development of verification strategies; evaluate and integrate cutting edge verification/emulation methodologies into the tool flow
Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production
Job Requirements:
Bachelor degree in Electrical Engineering or related area, MSEE is preferred.
3 years or above experience in ASIC/complex SoC design or verification.
Experience of SOC designs with embedded processor cores and their integration with other system components including memory subsystems and peripherals.
Familiar with HDL languages, simulation tools and testbench design, C/C++, scripting languages, experience with Specman/E and matlab is a plus
Good English and communication skills; will need frequent communication with foreign team.
IC验证工程师
DFT: DFT Engineer
Job Responsibilities:
Responsible for DFT sign off. Participate in driving new DFT methodology and solutions to improve quality, reliability and in system test and debug capability.
Generate tests which achieve highest possible component test coverage with lowest overhead.
Verify all DFT logics and test patterns with simulation and static timing analysis tool.
Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
Requirements:
3+ years experience
Good knowledge in Design for Test in general.
Understand the concepts of BIST, SCAN, JTAG, ATPG.
Experience in DFT design, Testability, and Reliability issues.
Hands on familiarity with various DFT analysis, and verification tools.
Hands on knowledge of simulation and verification debug tools.
Good knowledge of test engineering in terms of test program generation, ?
understanding of testers and associated hardware is a plus.
Working knowledge using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
Excellent written and ?verbal communications, team and people skills.
IC验证工程师
STA: STA Engineer
Responsibilities:
Pro-actively contribute in the research and development of Advanced IC Design flow and STA methodology.
Validate STA software (PrimeTime) in Advanced IC Design Flow
Responsible for developing, applying, and maintaining STA quality standards
Requirement:
Digital Circuit Design Static Timing Analysis
Tape-out experience of Advanced ASIC.Back-End design is a plus
Candidate must possess good Chinese and English communication skills
Candidate must have demonstrated strong problem solving skills, ability to work on large software systems
Highly motivated and passion to work is required. Detail focusing, performance oriented
IC验证工程师
PD: Physical Design Engineer
Responsibilities:
Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule,resource requirements and track backend schedule.
Requirements:
Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)
Hands on experience and detailed knowledge of Synopsys, Cadence or Magma(preferred) Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.
3+ years of direct experience on physical design.
Base:上海
有意的朋友简历请投至：wqbelinda@hotmail.com
Best regards!
belinda (Senior Consultant)
ShangHai wide-keen Consulting co.,Ltd.
Te l: 021-52731690-803
MSN: wqbelinda@hotmail.com |
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发表于 2011-08-11 10:06