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回复 2# calcm
Hardware Power On
@(#)OBP 4.17.1 2005/04/11 14:27 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CPU1 CPU3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done
Probing core system FRUs..
Probing Centerplane....part# 501-6790-02 serial# 007142
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 066387
Probing System RSC.....part# 501-5856-06 serial# 254539
Probing PwrDistBoard...part# 375-3006-05 serial# M75005
Probing PowerSupply0...part# 300-1480-05 serial# N49943
Probing PowerSupply1...part# 300-1480-05 serial# N44500
Probing FCAL BPlane0...part# 501-5822-04 serial# 068297
Probing GPTwo Slot A...No module detected
Probing GPTwo Slot B...part# 501-6164-02 serial# 052255
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
CPU rated speed 1200MHz; ECache 8MB 3.3ns Done
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU1 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU3 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00 Done
Setting system speed (and resetting)...
<*>
Set Speed Reset
@(#)OBP 4.17.1 2005/04/11 14:27 Sun Fire 4XX
Front Panel Keyswitch is in Diagnostic position.
System is initializing in Service Mode.
Online: CPU1 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: *CPU3 UltraSPARC III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Executing POST w/%o0 = 0000.1000.0101.4043
1:0>
1:0>@(#) Sun Fire[TM] V480/V490 POST 4.17.1 2005/04/11 14:37
/export/delivery/delivery/4.17/4.17.1/post4.17.0/Camelot/cstone/integrated (root)
1:0>Copyright 2005 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
1:0>Jump from OBP->POST.
1:0>diag-switch? configuration variable set TRUE.
1:0>Keyswitch in DIAGNOSTIC POSITION.
1:0>Diag level set to MAX.
1:0>Verbosity level set to MAX.
1:0>MFG scrpt mode set NORM
1:0>I/O port set to serial TTYA.
1:0>
1:0>Start selftest...
1:0>CPUs present in system: 1:0 3:0
1:0>Test CPU(s).....
1:0>Init CPU
1:0> UltraSparc_III_plus Version 11.1
1:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0> Size = 00000000.00800000...
1:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
3:0>Init CPU
3:0> UltraSparc_III_plus Version 11.1
3:0>DMMU Registers Access
3:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB TAGS Access
3:0>IMMU Registers Access
3:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB TAGS Access
3:0>Probe Ecache
3:0> Size = 00000000.00800000...
3:0>Ecache Data Bitwalk
3:0>Ecache Address Bitwalk
3:0>Scrub and Setup Ecache
3:0>Setup and Enable DMMU
3:0>Setup DMMU Miss Handler
3:0>Test and Init Temp Mailbox
1:0>Init Scan/I2C.....
1:0>Initializing Scan Database
1:0>Mask DAR errors off
1:0>Init CDX DTL
1:0>Init DAR DTL
1:0>Enable Partial DAR error
1:0>Init DCS DTL
1:0>Init I2C
1:0>Unquiesce Safari
然后到这就停了。。 |
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