PCI控制器配置实例

pauloxu

1.PCI interface scheme

The MPC8321 has one 32bit PCI BUS. The bus frequency runs up to 66MHz clock. In our design the MPC8321 is
operates as a HOST & Arbiter on the BUS. Because the BCM56228 only can run under 50MHz, so the PCI frequency
runs under 33MHz.

2.寄存器定义

1. #define M83XXPCI_LAWBAR0 0x60
   
2. #define M83XXPCI_LAWAR0 0x64
   
3. #define M83XXPCI_LAWBAR1 0x68
   
4. #define M83XXPCI_LAWAR1 0x6C
   
5. 
   
6. #define M83XXPCI_LAWAR_ENABLE 0x80000000
   
7. 
   
8. /* LAWAR SIZE Settings */
   
9. #define M83XXPCI_LAWAR_SIZE_4KB 0x0000000B
   
10. #define M83XXPCI_LAWAR_SIZE_8KB 0x0000000C
    
11. #define M83XXPCI_LAWAR_SIZE_16KB 0x0000000D
    
12. #define M83XXPCI_LAWAR_SIZE_32KB 0x0000000E
    
13. #define M83XXPCI_LAWAR_SIZE_64KB 0x0000000F
    
14. #define M83XXPCI_LAWAR_SIZE_128KB 0x00000010
    
15. #define M83XXPCI_LAWAR_SIZE_256KB 0x00000011
    
16. #define M83XXPCI_LAWAR_SIZE_512KB 0x00000012
    
17. #define M83XXPCI_LAWAR_SIZE_1MB 0x00000013
    
18. #define M83XXPCI_LAWAR_SIZE_2MB 0x00000014
    
19. #define M83XXPCI_LAWAR_SIZE_4MB 0x00000015
    
20. #define M83XXPCI_LAWAR_SIZE_8MB 0x00000016
    
21. #define M83XXPCI_LAWAR_SIZE_16MB 0x00000017
    
22. #define M83XXPCI_LAWAR_SIZE_32MB 0x00000018
    
23. #define M83XXPCI_LAWAR_SIZE_64MB 0x00000019
    
24. #define M83XXPCI_LAWAR_SIZE_128MB 0x0000001A
    
25. #define M83XXPCI_LAWAR_SIZE_256MB 0x0000001B
    
26. #define M83XXPCI_LAWAR_SIZE_512MB 0x0000001C
    
27. #define M83XXPCI_LAWAR_SIZE_1GB 0x0000001D
    
28. #define M83XXPCI_LAWAR_SIZE_2GB 0x0000001E
    
29. 
    
30. 
    
31. #ifndef PCI_MSTR_MEM_BUS
    
32. #define PCI_MSTR_MEM_BUS 0x40000000 /* align on 512 MB */
    
33. #endif
    
34. 
    
35. 
    
36. /* static file scope locals */
    
37. 
    
38. #define COMMAND_REGISTER_OFFSET 0x4
    
39. #define COMMAND_REGISTER_WIDTH 0x2
    
40. #define BRIDGE_BAR0_OFFSET 0x10
    
41. #define BRIDGE_BAR0_WIDTH 0x4
    
42. 
    
43. /* Control and Status registers */
    
44. #define M83XXPCI_ESR_REG    0x500 /* Error Status Register */
    
45. #define M83XXPCI_GCR_REG    0x520 /* General Control Register */
    
46. #define M83XXPCI_ECR_REG    0x524    /* Error Control Register */
    
47. #define M83XXPCI_GSR_REG    0x528    /* General Status Register */
    
48. 
    
49. 
    
50. /* TBD ALL the registers for PCI Bridge */
    
51. /* configuration space reg and int ack */
    
52. #define M83XXPCI_CONF_ADDR 0x300
    
53. #define M83XXPCI_CONF_DATA 0x304
    
54. 
    
55. /* Outbound translation and base address registers */
    
56. #define M83XXPCI_OB_TRANS_ADRS_REG0     0x400
    
57. #define M83XXPCI_OB_BASE_ADRS_REG0     0x408
    
58. #define M83XXPCI_OB_TRANS_ADRS_REG1     0x418
    
59. #define M83XXPCI_OB_BASE_ADRS_REG1     0x420
    
60. #define M83XXPCI_OB_TRANS_ADRS_REG2     0x430
    
61. #define M83XXPCI_OB_BASE_ADRS_REG2     0x438
    
62. #define M83XXPCI_OB_TRANS_ADRS_REG3     0x448
    
63. #define M83XXPCI_OB_BASE_ADRS_REG3     0x450
    
64. #define M83XXPCI_OB_TRANS_ADRS_REG4     0x460
    
65. #define M83XXPCI_OB_BASE_ADRS_REG4     0x468
    
66. 
    
67. /* Outbound attributes register definitions */
    
68. #define M83XXPCI_OB_ATTR_REG0 0x410
    
69. #define M83XXPCI_OB_ATTR_REG1 0x428
    
70. #define M83XXPCI_OB_ATTR_REG2 0x440
    
71. #define M83XXPCI_OB_ATTR_REG3 0x458
    
72. #define M83XXPCI_OB_ATTR_REG4 0x470
    
73. 
    
74. /* Outbound Comparison mask register defines */
    
75. 
    
76. #define M83XXPCI_OB_WINDOW_ENABLE_BIT 0x80000000
    
77. #define M83XXPCI_OB_ATTR_IO_BIT 0x40000000
    
78. #define M83XXPCI_OB_ATTR_SE_BIT 0x20000000
    
79. #define M83XXPCI_OB_ATTR_WS_4K 0x000FFFFF
    
80. #define M83XXPCI_OB_ATTR_WS_8K 0x000FFFFE
    
81. #define M83XXPCI_OB_ATTR_WS_16K 0x000FFFFC
    
82. #define M83XXPCI_OB_ATTR_WS_32K 0x000FFFF8
    
83. #define M83XXPCI_OB_ATTR_WS_64K 0x000FFFF0
    
84. #define M83XXPCI_OB_ATTR_WS_128K 0x000FFFE0
    
85. #define M83XXPCI_OB_ATTR_WS_256K 0x000FFFC0
    
86. #define M83XXPCI_OB_ATTR_WS_512K 0x000FFF80
    
87. #define M83XXPCI_OB_ATTR_WS_1M 0x000FFF00
    
88. #define M83XXPCI_OB_ATTR_WS_2M 0x000FFE00
    
89. #define M83XXPCI_OB_ATTR_WS_4M 0x000FFC00
    
90. #define M83XXPCI_OB_ATTR_WS_8M 0x000FF800
    
91. #define M83XXPCI_OB_ATTR_WS_16M 0x000FF000
    
92. #define M83XXPCI_OB_ATTR_WS_32M 0x000FE000
    
93. #define M83XXPCI_OB_ATTR_WS_64M 0x000FC000
    
94. #define M83XXPCI_OB_ATTR_WS_128M 0x000F8000
    
95. #define M83XXPCI_OB_ATTR_WS_256M 0x000F0000
    
96. #define M83XXPCI_OB_ATTR_WS_512M 0x000E0000
    
97. #define M83XXPCI_OB_ATTR_WS_1G 0x000C0000
    
98. #define M83XXPCI_OB_ATTR_WS_2G 0x00080000
    
99. #define M83XXPCI_OB_ATTR_WS_4G 0x00000000
    
100. 
     
101. 
     
102. 
     
103. /* Inbound translation and base address registers */
     
104. #define M83XXPCI_IB_TRANS_ADRS_REG0          0x568
     
105. #define M83XXPCI_IB_BASE_ADRS_REG0         0x570
     
106. #define M83XXPCI_IB_ATTR_REG0 0x578
     
107. #define M83XXPCI_IB_TRANS_ADRS_REG1          0x550
     
108. #define M83XXPCI_IB_BASE_ADRS_REG1     0x558     
     
109. #define M83XXPCI_IB_ATTR_REG1 0x560
     
110. #define M83XXPCI_IB_TRANS_ADRS_REG2          0x538
     
111. #define M83XXPCI_IB_BASE_ADRS_REG2         0x540
     
112. #define M83XXPCI_IB_ATTR_REG2 0x548
     
113. 
     
114. 
     
115. /* Inbound Window Attribute register defines */
     
116. 
     
117. #define M83XXPCI_IB_WINDOW_ENABLE_BIT 0x80000000
     
118. #define M83XXPCI_IB_ATTR_PREFETCHABLE 0x20000000
     
119. #define M83XXPCI_IB_ATTR_RTT_READ_NO_SNOOP 0x00040000
     
120. #define M83XXPCI_IB_ATTR_RTT_READ_SNOOP 0x00050000
     
121. #define M83XXPCI_IB_ATTR_RTT_WRITE_NO_SNOOP 0x00004000
     
122. #define M83XXPCI_IB_ATTR_RTT_WRITE_SNOOP 0x00005000
     
123. #define M83XXPCI_IB_ATTR_IWS_4K 0x0000000B
     
124. #define M83XXPCI_IB_ATTR_IWS_8K 0x0000000C
     
125. #define M83XXPCI_IB_ATTR_IWS_16K 0x0000000D
     
126. #define M83XXPCI_IB_ATTR_IWS_32K 0x0000000E
     
127. #define M83XXPCI_IB_ATTR_IWS_64K 0x0000000F
     
128. #define M83XXPCI_IB_ATTR_IWS_128K 0x00000010
     
129. #define M83XXPCI_IB_ATTR_IWS_256K 0x00000011
     
130. #define M83XXPCI_IB_ATTR_IWS_512K 0x00000012
     
131. #define M83XXPCI_IB_ATTR_IWS_1M 0x00000013
     
132. #define M83XXPCI_IB_ATTR_IWS_2M 0x00000014
     
133. #define M83XXPCI_IB_ATTR_IWS_4M 0x00000015
     
134. #define M83XXPCI_IB_ATTR_IWS_8M 0x00000016
     
135. #define M83XXPCI_IB_ATTR_IWS_16M 0x00000017
     
136. #define M83XXPCI_IB_ATTR_IWS_32M 0x00000018
     
137. #define M83XXPCI_IB_ATTR_IWS_64M 0x00000019
     
138. #define M83XXPCI_IB_ATTR_IWS_128M 0x0000001A
     
139. #define M83XXPCI_IB_ATTR_IWS_256M 0x0000001B
     
140. #define M83XXPCI_IB_ATTR_IWS_512M 0x0000001C
     
141. #define M83XXPCI_IB_ATTR_IWS_1G 0x0000001D
     
142. #define M83XXPCI_IB_ATTR_IWS_2G 0x0000001E
     
143. 
     
144. /* Encoding direction defines */
     
145. #define M83XXPCI_IN_BOUND    0
     
146. #define M83XXPCI_OUT_BOUND 1
     
147. 
     
148. 
     
149. #define PCI_SNOOP_ENABLE 0x40000000
     
150. #define PCI_PREFETCHABLE 0x20000000
     
151. 
     
152. /* PCI error Registers */
     
153. 
     
154. /* Comand status register defines */
     
155. #define BUS_MASTER_ENABLE_BIT 0x4
     
156. #define MEMORY_SPACE_ACCESS_ENABLE_BIT 0x2

3.核心数据结构

1. typedef struct m83xxPciDrvCtrl
   
2.     {
   
3.     VXB_DEVICE_ID    pInst;
   
4.     void *    handle;
   
5.     UINT32    magicNumber1;
   
6.     UINT32    magicNumber2;
   
7.     int pciMaxBus;    /* Max number of sub-busses */
   
8.     
   
9.     void * mem32Addr;
   
10.     UINT32 mem32Size;
    
11.     void * memIo32Addr;
    
12.     UINT32 memIo32Size;
    
13.     void * io32Addr;
    
14.     UINT32 io32Size;
    
15. 
    
16.     void *    pimmrBase;
    
17.     void *    mstrMemBus;
    
18.     void *    lclMemAddr;
    
19.     UINT32    lclMemMapSize;
    
20. 
    
21.     UINT32 tgtIf;
    
22.     UINT32 owAttrMem;
    
23.     UINT32 owAttrMemIo;
    
24.     UINT32 owAttrIo;
    
25.     UINT32 iwAttr;
    
26.     UINT32 singleLawBar;
    
27.     UINT32 singleLawBarSize;
    
28.     UINT32 pciExpressHost;
    
29.     UINT32 autoConfig;
    
30.     UINT32* lawbar; /* LAWBAR address */
    
31.     UINT32* lawar; /* LAWAR address*/
    
32.     UINT32 lawarAttr; /* LAWAR attributes */
    
33.     BOOL    initDone;
    
34. 
    
35.     struct vxbPciConfig *pPciConfig;
    
36.     struct vxbPciInt *pIntInfo;
    
37.     struct hcfDevice * pHcf;
    
38.     } M83XXPCI_DRV_CTRL;

4.配置空间寄存器的读写

1. 一.读
   
2. LOCAL STATUS m83xxPciMethodCfgRead
   
3.     (
   
4.     VXB_DEVICE_ID pInst,    /* device info */
   
5.     UINT8     busNo,    /* bus number */
   
6.     UINT8     deviceNo,    /* device number */
   
7.     UINT8     funcNo,    /* function number */
   
8.     UINT32     offset,    /* offset into the configuration space */
   
9.     UINT32     width,    /* width to be read */
   
10.     void *     pData    /* data buffer read from the offset */
    
11.     )
    
12.     {
    
13.     struct m83xxPciDrvCtrl *    pDrvCtrl;
    
14.     int                key;
    
15.     STATUS            retStat = OK;
    
16. 
    
17.     if ((busNo == 0) && (deviceNo == 12))
    
18.         return (ERROR);
    
19. 
    
20.     pDrvCtrl = pInst->pDrvCtrl;
    
21. 
    
22.     key = intCpuLock ();
    
23. 
    
24.     switch (width)
    
25.         {
    
26.         case 1: /* byte */
    
27.             pciOutLong (pInst,M83XXPCI_CONF_ADDR,
    
28.                         vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
    
29.                         (offset & 0xfc) | 0x80000000);
    
30. 
    
31.             *(UINT8 *)pData = pciInByte (pInst,
    
32.                      M83XXPCI_CONF_DATA + (offset & 0x3));
    
33. 
    
34.             break;
    
35. 
    
36.         case 2: /* word */
    
37.             pciOutLong (pInst,M83XXPCI_CONF_ADDR,
    
38.                         vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
    
39.                         (offset & 0xfc) | 0x80000000);
    
40. 
    
41.             *(UINT16 *)pData = pciInWord (pInst,
    
42.                      M83XXPCI_CONF_DATA + (offset & 0x2));
    
43. 
    
44.             break;
    
45. 
    
46.         case 4: /* long */
    
47.             pciOutLong (pInst,M83XXPCI_CONF_ADDR,
    
48.                         vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
    
49.                         (offset & 0xfc) | 0x80000000);
    
50. 
    
51.             *(UINT32 *)pData = pciInLong (pInst, M83XXPCI_CONF_DATA);
    
52. 
    
53.             break;
    
54. 
    
55.         default:
    
56.             retStat = ERROR;
    
57. 
    
58.             break;
    
59.         }
    
60. 
    
61.     intCpuUnlock (key);
    
62. 
    
63.     return (retStat);
    
64.     }
    
65. 
    
66. 二.写
    
67. LOCAL STATUS m83xxPciMethodCfgWrite
    
68.     (
    
69.     VXB_DEVICE_ID pInst,    /* device info */
    
70.     UINT8     busNo,    /* bus number */
    
71.     UINT8     deviceNo,    /* device number */
    
72.     UINT8     funcNo,    /* function number */
    
73.     UINT32     offset,    /* offset into the configuration space */
    
74.     UINT32     width,    /* width to be read */
    
75.     void *     pData    /* data buffer write to the offset */
    
76.     )
    
77.     {
    
78.     struct m83xxPciDrvCtrl *    pDrvCtrl;
    
79.     int                key;
    
80.     STATUS            retStat = OK;
    
81. 
    
82.     if ((busNo == 0) && (deviceNo == 12))
    
83.         return (ERROR);
    
84. 
    
85.     pDrvCtrl = pInst->pDrvCtrl;
    
86. 
    
87.     key = intCpuLock ();
    
88. 
    
89.     switch (width)
    
90.         {
    
91.         case 1: /* byte */
    
92.             pciOutLong (pInst, M83XXPCI_CONF_ADDR,
    
93.                         vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
    
94.                         (offset & 0xfc) | 0x80000000);
    
95. 
    
96.             pciOutByte (pInst, (M83XXPCI_CONF_DATA + (offset & 0x3)),
    
97.             *(UINT8*)pData);
    
98. 
    
99.             break;
    
100. 
     
101.         case 2: /* word */
     
102.             pciOutLong (pInst, M83XXPCI_CONF_ADDR,
     
103.                           vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
     
104.                           (offset & 0xfc) | 0x80000000);
     
105. 
     
106.             pciOutWord (pInst, (M83XXPCI_CONF_DATA + (offset & 0x2)),
     
107.             *(UINT16*)pData);
     
108. 
     
109.             break;
     
110. 
     
111.         case 4: /* long */
     
112.             pciOutLong (pInst,M83XXPCI_CONF_ADDR,
     
113.                           vxbPciConfigBdfPack (busNo, deviceNo, funcNo) |
     
114.                           (offset & 0xfc) | 0x80000000);
     
115. 
     
116.             pciOutLong (pInst, M83XXPCI_CONF_DATA, *(UINT32*)pData);
     
117. 
     
118.             break;
     
119. 
     
120.         default:
     
121.      retStat = ERROR;
     
122. 
     
123.      break;
     
124.         }
     
125. 
     
126.     intCpuUnlock (key);
     
127. 
     
128.     return (retStat);
     
129.     }

5.PCI bridge 初始化

1. LOCAL STATUS m83xxPciBridgeInit(VXB_DEVICE_ID pInst)
   
2.     {
   
3.     UINT16 tempWord;
   
4.     UINT32 tempLong;
   
5.     struct m83xxPciDrvCtrl * pDrvCtrl;
   
6. #ifndef    VXB_LEGACY_ACCESS
   
7.     PCI_HARDWARE pciDev;
   
8.     PCI_HARDWARE * pPciDev = (PCI_HARDWARE *) &pciDev;
   
9.     pPciDev->pciBus = 0;
   
10.     pPciDev->pciDev = 0;
    
11.     pPciDev->pciFunc = 0;
    
12. #endif    /* !VXB_LEGACY_ACCESS */
    
13. 
    
14.     pDrvCtrl = pInst->pDrvCtrl;
    
15. 
    
16.     if(isColdBoot())
    
17.     {
    
18.      M83XXPCI_REG_WRITE32(M83XXPCI_GCR_REG, 0x1); /* Clear PCI reset */
    
19. 
    
20.      /* Allow time for PCI Bus to come out of reset */
    
21.      {
    
22.      volatile int i;
    
23.      for (i = 0 ; i < 0x80000 ; i++)
    
24.      WRS_ASM("isync");
    
25.      }
    
26.     
    
27.      M83XXPCI_REG_WRITE32(M83XXPCI_GCR_REG, 0x0); /* PCI reset */
    
28. 
    
29.      /* Allow time for PCI Bus to reset */
    
30.      {
    
31.      volatile int i;
    
32.      for (i = 0 ; i < 0x80000 ; i++)
    
33.      WRS_ASM("isync");
    
34.      }
    
35. 
    
36.      M83XXPCI_REG_WRITE32(M83XXPCI_GCR_REG, 0x1); /* Clear PCI reset */
    
37. 
    
38.      /* Allow time for PCI Bus to come out of reset */
    
39.      {
    
40.      volatile int i;
    
41.      for (i = 0 ; i < 0x80000 ; i++)
    
42.      WRS_ASM("isync");
    
43.      }
    
44.     }
    
45. 
    
46.     M83XXPCI_REG_READ32(M83XXPCI_GCR_REG,tempLong);
    
47. 
    
48.     /* Initialize LAWBAR/LAWAR for PCI */
    
49.     *pDrvCtrl->lawbar = (UINT32)pDrvCtrl->mem32Addr;
    
50. 
    
51.     *pDrvCtrl->lawar = (UINT32)pDrvCtrl->lawarAttr;
    
52. 
    
53.     M83XXPCI_REG_WRITE32(M83XXPCI_ECR_REG, 0x0); /* Generate interrupt if PCI error and ESR set*/
    
54. 
    
55.     M83XXPCI_REG_WRITE32(M83XXPCI_ESR_REG, 0xffffffff); /* Clear status */
    
56. 
    
57.     /* Set outbound translation window addresses */
58. 
    
59. /* 设置内存空间基址寄存器 */
    
60. #ifdef    VXB_LEGACY_ACCESS
    
61.     m83xxPciMethodCfgWrite(pInst, 0,0,0,
    
62.                            PCI_CFG_BASE_ADDRESS_0,
    
63.                            0x4,
    
64.                            (void *)&pDrvCtrl->pimmrBase);
    
65. #else    /* VXB_LEGACY_ACCESS */
    
66.     m83xxPciMethodDevCfgWrite(pInst, pPciDev,
    
67.                               PCI_CFG_BASE_ADDRESS_0,
    
68.                               0x4,
    
69.                               (UINT32)pDrvCtrl->pimmrBase);
    
70. #endif    /* VXB_LEGACY_ACCESS */
    
71.     /* 设置MPC内部mem基地址 */
    
72.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_BASE_ADRS_REG0, pDrvCtrl->mem32Addr >> 12);
    
73.     /* 设置PCI总线地址基址 */
    
74.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_TRANS_ADRS_REG0, pDrvCtrl->mem32Addr >> 12);
    
75.     /* 设置MPC内部memIO基地址 */
    
76.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_BASE_ADRS_REG1, pDrvCtrl->memIo32Addr >> 12);
    
77.     /* 设置PCI总线memIO地址基址 */
    
78.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_TRANS_ADRS_REG1, pDrvCtrl->memIo32Addr >> 12);
    
79.     /* 设置MPC内部IO基地址 */
    
80.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_BASE_ADRS_REG2, pDrvCtrl->io32Addr >> 12);
    
81.    /* 设置PCI总线IO地址基址 */
    
82.     M83XXPCI_REG_WRITE32(M83XXPCI_OB_TRANS_ADRS_REG2, pDrvCtrl->io32Addr >> 12);
    
83. 
    
84.     /* Switch on the outbound translation windows */
    
85.     /* 设置outbound窗口属性 */
    
86.     if(pDrvCtrl->owAttrMem == 0)
    
87.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG0, M83XXPCI_OB_WINDOW_ENABLE_BIT |
    
88.                                                     M83XXPCI_OB_ATTR_SE_BIT |
    
89.                                                     M83XXPCI_OB_ATTR_WS_128M);
    
90.     else
    
91.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG0, pDrvCtrl->owAttrMem);
    
92.         
    
93.     if(pDrvCtrl->owAttrMemIo == 0)
    
94.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG1, M83XXPCI_OB_WINDOW_ENABLE_BIT |
    
95.                                                     M83XXPCI_OB_ATTR_SE_BIT |
    
96.                                                     M83XXPCI_OB_ATTR_WS_64M);
    
97.     else
    
98.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG1, pDrvCtrl->owAttrMemIo);
    
99.         
    
100.     if (pDrvCtrl->owAttrIo == 0)
     
101.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG2, M83XXPCI_OB_WINDOW_ENABLE_BIT |
     
102.                                                     M83XXPCI_OB_ATTR_IO_BIT |
     
103.                                                     M83XXPCI_OB_ATTR_WS_64M);
     
104.     else
     
105.         M83XXPCI_REG_WRITE32(M83XXPCI_OB_ATTR_REG2, pDrvCtrl->owAttrIo);
     
106.         
     
107.     /* 设置PCI总线基地址 */
     
108.     M83XXPCI_REG_WRITE32(M83XXPCI_IB_BASE_ADRS_REG0, ((UINT32)pDrvCtrl->mstrMemBus>>12) & 0xfffff);
     
109.         
     
110.     /* 设置mpc存储器基地址 */
     
111.     M83XXPCI_REG_WRITE32(M83XXPCI_IB_TRANS_ADRS_REG0, ((UINT32)pDrvCtrl->lclMemAddr>>12) & 0xfffff);
     
112.         
     
113.     /* 设置inbound窗口属性 */
     
114.     M83XXPCI_REG_WRITE32(M83XXPCI_IB_ATTR_REG0, M83XXPCI_IB_WINDOW_ENABLE_BIT |
     
115.                                                 M83XXPCI_IB_ATTR_PREFETCHABLE |
     
116.                                                 M83XXPCI_IB_ATTR_RTT_READ_SNOOP |
     
117.                                                 M83XXPCI_IB_ATTR_RTT_WRITE_SNOOP |
     
118.                                                 M83XXPCI_IB_ATTR_IWS_256M);
     
119. 
     
120.     /* No need to enable inbound memIo */
     
121.     M83XXPCI_REG_WRITE32(M83XXPCI_IB_ATTR_REG1, 0);
     
122. 
     
123.     /* No need to enable inboune IO */
     
124.     M83XXPCI_REG_WRITE32(M83XXPCI_IB_ATTR_REG2, 0);
     
125. 
     
126. 
     
127.     /* configure the bridge as bus master */
     
128. 
     
129.     tempWord = PCI_CMD_IO_ENABLE | PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE;
     
130. 
     
131. #ifdef    VXB_LEGACY_ACCESS
     
132.     m83xxPciMethodCfgWrite(pInst, 0,0,0,
     
133.                            COMMAND_REGISTER_OFFSET,
     
134.                            COMMAND_REGISTER_WIDTH,
     
135.                            (void *)&tempWord);
     
136. #else    /* VXB_LEGACY_ACCESS */
     
137.     m83xxPciMethodDevCfgWrite(pInst, pPciDev,
     
138.                               COMMAND_REGISTER_OFFSET,
     
139.                               COMMAND_REGISTER_WIDTH,
     
140.                               (UINT32)tempWord);
     
141. #endif    /* VXB_LEGACY_ACCESS */
     
142. 
     
143.     return(OK);
     
144.     }