SUN3500启动故障，请教各位高手

leon333

Hardware Power ON\r\n\r\n@(#) Ultra Enterprise 3.2 Version 24 created 1999/12/23 17:31\r\nCPU = 0000.0000.0000.0006\r\nProbing keyboard Done\r\n\r\n3,0>;\r\n3,0>;@(#) POST 3.9.24 1999/12/23 17:35\r\n3,1>;\r\n3,0>;\r\n    SelfTest Initializing (Diag Level 10, ENV 0000ff01) IMPL 0011 MASK a0\r\n3,1>;@(#) POST 3.9.24 1999/12/23 17:35\r\n3,0>;Board 3 CPU FPROM Test\r\n3,1>;\r\n    SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK a0\r\n3,0>;Board 3 Basic CPU Test\r\n3,0>;    Set CPU UPA Config and Init SDB Data\r\n3,0>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n3,0>;Board 3 MMU Enable Test\r\n3,0>;    DMMU Init\r\n3,0>;    IMMU Init\r\n3,0>;    Mapping Selftest Enabling MMUs\r\n3,0>;Board 3 Ecache Test\r\n3,0>;    Ecache Probe\r\n3,0>;    Ecache Tags\r\n3,1>;Board 3 CPU FPROM Test\r\n3,1>;Board 3 Basic CPU Test\r\n3,1>;    Set CPU UPA Config and Init SDB Data\r\n3,1>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n3,1>;Board 3 MMU Enable Test\r\n3,1>;    DMMU Init\r\n3,1>;    IMMU Init\r\n3,1>;    Mapping Selftest Enabling MMUs\r\n3,1>;Board 3 Ecache Test\r\n3,1>;    Ecache Probe\r\n3,1>;    Ecache Tags\r\n3,0>;    Ecache Quick Verify\r\n3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3\r\n3,0>;Component under test: Board 3 CPU 0\r\n3,0>;    RAM compare error,\r\n        index    1\r\n        expected 55555555.55555555\r\n        observed 00005555.00005555\r\n        xor      55550000.55550000\r\n3,1>;    Ecache Quick Verify\r\n3,1>;    Ecache Init\r\n3,0>;\r\n         *** Aborting Test List due to severe error ***\r\n\r\n3,0>;Deconfiguring CPU MID 6\r\n3,1>;    Ecache RAM\r\n3,1>;    Ecache Address Line\r\n3,1>;    Configure Ecache Limit\r\n3,1>;Ecache Size = 00800000,  Limited to 00800000\r\n3,1>;Board 3 FPU Functional Test\r\n3,1>;    FPU Enable\r\n3,1>;Board 3 Board Master Select Test\r\n3,1>;    Selecting a Board Master\r\n3,1>;Board 3 FireHose Devices Test\r\n3,1>;Board 3 Address Controller Test\r\n3,1>;    AC Initialization\r\n3,1>;    AC DTAG Init\r\n3,1>;Board 3 Dual Tags Test\r\n3,1>;    AC DTAG Init\r\n3,1>;Board 3 FireHose Controller Test\r\n3,1>;    FHC Initialization\r\n3,1>;Board 3 JTAG Test\r\n3,1>;    Verify System Board Scan Ring\r\n3,1>;Board 3 Centerplane Test\r\n3,1>;    Centerplane Join\r\n3,1>;Setting JTAG Master\r\n3,1>;Clear JTAG Master\r\n3,1>;Board 3 Setup Cache Size Test\r\n3,1>;    Setting Up Cache Size\r\n3,1>;Board 3 System Master Select Test\r\n3,1>;    Setting System Master\r\n3,1>OST Master Selected (JTAG,CENTRAL)\r\n3,1>;Board 16 Clock Board Test\r\n3,1>;    Clock Board Initialization\r\n3,1>;    Clock Board Temperature Check\r\n3,1>;Board 16 Clock Board Serial Ports Test\r\n3,1>;Board 16 NVRAM Devices Test\r\n3,1>;    M48T59 (TOD) Init\r\n3,1>;Board 3 System Board Probe  Test\r\n3,1>;    Probing all CPU/Memory BDA\r\n3,1>;    Probing System Boards\r\n3,1>;    Probing CPU Module JTAG Rings\r\n3,1>;Setting System Clock Frequency\r\n3,1>;    CPU mid 6 Checked in FAILED\r\n3,1>;    CPU Module mid 7 Checked in OK (speed code = 3)\r\n3,1>; ******** Clock Reset - retesting\r\n3,1>;System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400\r\n3,1>;\r\n3,1>;@(#) POST 3.9.24 1999/12/23 17:35\r\n3,1>;\r\n    SelfTest Initializing (Diag Level 40, ENV 0000ff81) IMPL 0011 MASK a0\r\n3,1>;Board 3 CPU FPROM Test\r\n3,1>;    CPU/Memory Board FPROM Checksum Test\r\n3,0>;\r\n3,0>;@(#) POST 3.9.24 1999/12/23 17:35\r\n3,0>;\r\n    SelfTest Initializing (Diag Level 40, ENV 0000ff81) IMPL 0011 MASK a0\r\n3,0>;Board 3 CPU FPROM Test\r\n3,0>;    CPU/Memory Board FPROM Checksum Test\r\n3,1>;Board 3 Basic CPU Test\r\n3,1>;    FPU Registers and Data Path Test\r\n3,1>;    Instruction Cache Tag RAM Test\r\n3,0>;Board 3 Basic CPU Test\r\n3,0>;    FPU Registers and Data Path Test\r\n3,1>;    Instruction Cache Instruction RAM Test\r\n3,0>;    Instruction Cache Tag RAM Test\r\n3,0>;    Instruction Cache Instruction RAM Test\r\n3,1>;    Instruction Cache Next Field RAM Test\r\n3,0>;    Instruction Cache Next Field RAM Test\r\n3,1>;    Instruction Cache Pre-decode RAM Test\r\n3,0>;    Instruction Cache Pre-decode RAM Test\r\n3,1>;    Data Cache RAM Test\r\n3,0>;    Data Cache RAM Test\r\n3,1>;    Data Cache Tags Test\r\n3,1>;    DMMU Registers Access Test\r\n3,0>;    Data Cache Tags Test\r\n3,1>;    DMMU TLB DATA RAM Access Test\r\n3,1>;    DMMU TLB TAGS Access Test\r\n3,1>;    IMMU Registers Access Test\r\n3,1>;    IMMU TLB DATA RAM Access Test\r\n3,1>;    IMMU TLB TAGS Access Test\r\n3,1>;    Set CPU UPA Config and Init SDB Data\r\n3,1>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n3,0>;    DMMU Registers Access Test\r\n3,1>;Board 3 MMU Enable Test\r\n3,1>;    DMMU Init\r\n3,1>;    IMMU Init\r\n3,1>;    Mapping Selftest Enabling MMUs\r\n3,1>;Board 3 Ecache Test\r\n3,1>;    Ecache Probe\r\n3,0>;    DMMU TLB DATA RAM Access Test\r\n3,1>;    Ecache Tags\r\n3,0>;    DMMU TLB TAGS Access Test\r\n3,0>;    IMMU Registers Access Test\r\n3,0>;    IMMU TLB DATA RAM Access Test\r\n3,0>;    IMMU TLB TAGS Access Test\r\n3,0>;    Set CPU UPA Config and Init SDB Data\r\n3,0>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n3,0>;Board 3 MMU Enable Test\r\n3,0>;    DMMU Init\r\n3,0>;    IMMU Init\r\n3,0>;    Mapping Selftest Enabling MMUs\r\n3,0>;Board 3 Ecache Test\r\n3,0>;    Ecache Probe\r\n3,0>;    Ecache Tags\r\n3,1>;    Ecache Quick Verify\r\n3,1>;    Ecache Init\r\n3,0>;    Ecache Quick Verify\r\n3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3\r\n3,0>;Component under test: Board 3 CPU 0\r\n3,0>;    RAM compare error,\r\n        index    1\r\n        expected 55555555.55555555\r\n        observed 00005555.00005555\r\n        xor      55550000.55550000\r\n3,0>;\r\n         *** Aborting Test List due to severe error ***\r\n\r\n3,0>;Deconfiguring CPU MID 6\r\n3,1>;    Ecache RAM\r\n3,1>;    Ecache 6N RAM Pattern Test\r\n3,1>;    Ecache Address Line\r\n3,1>;    Configure Ecache Limit\r\n3,1>;Ecache Size = 00800000,  Limited to 00800000\r\n3,1>;Board 3 FPU Functional Test\r\n3,1>;    FPU Enable\r\n3,1>;Board 3 Board Master Select Test\r\n3,1>;    Selecting a Board Master\r\n3,1>;Board 3 FireHose Devices Test\r\n3,1>;    PROM Datapath Test\r\n3,1>;    FHC CPU SRAM Test\r\n3,1>;Board 3 Address Controller Test\r\n3,1>;    AC Registers Test\r\n3,1>;    AC Initialization\r\n3,1>;    Memory Registers  Test\r\n3,1>;    Memory Registers Initialization Test\r\n3,1>;    AC DTAG Init\r\n3,1>;Board 3 Dual Tags Test\r\n3,1>;    AC DTAG Test\r\n3,1>;    AC DTAG Init\r\n3,1>;Board 3 FireHose Controller Test\r\n3,1>;    FHC Initialization\r\n3,1>;Board 3 JTAG Test\r\n3,1>;    Verify System Board Scan Ring\r\n3,1>;Board 3 Centerplane Test\r\n3,1>;    Centerplane and Arbiter Check Test\r\n3,1>;Setting JTAG Master\r\n3,1>;Clear JTAG Master\r\n3,1>;    Centerplane Join\r\n3,1>;Setting JTAG Master\r\n3,1>;Clear JTAG Master\r\n3,1>;Board 3 Setup Cache Size Test\r\n3,1>;    Setting Up Cache Size\r\n3,1>;Board 3 System Master Select Test\r\n3,1>;    Setting System Master\r\n3,1>OST Master Selected (JTAG,CENTRAL)\r\n3,1>;Board 16 Clock Board Test\r\n3,1>;    Clock Board Registers Test\r\n3,1>;    Clock Board Initialization\r\n3,1>;    Clock Board Temperature Check\r\n3,1>;Board 16 Clock Board Serial Ports Test\r\n3,1>;    85C30 Register Test\r\n3,1>;    85C30 Serial Ports Test\r\n3,1>;    Keyboard Loopback\r\n3,1>;    Mouse Loopback\r\n3,1>;    Serial Port B Loopback\r\n3,1>;    Remote Serial Port A Loopback\r\n3,1>;    Remote Serial Port B Loopback\r\n3,1>;Board 16 NVRAM Devices Test\r\n3,1>;    M48T59 (TOD) Init\r\n3,1>;    M48T59 (TOD) Functional Part 1 Test\r\n3,1>;    NVRAM(Non-Destructive) Test\r\n3,1>;Board 3 System Board Probe  Test\r\n3,1>;    Probing all CPU/Memory BDA\r\n3,1>;    Probing System Boards\r\n3,1>;    Probing CPU Module JTAG Rings\r\n\r\n每次到这就无响应了，重启若干次无效，求教。

paradisegame

先看~cpu板是不是没插好~如果不是，那么荣幸的告诉你可以换一个再来试试看了~！！！内存再看看！3500比较脆弱~cpu板经常容易出问题~

Philmoon

注意这一段：\r\n3,0>;ERROR: TEST=Ecache,SUBTEST=Ecache Quick Verify ID=4.3 \r\n3,0>;Component under test: Board 3 CPU 0 \r\n3,0>; RAM compare error, \r\nindex 1 \r\nexpected 55555555.55555555 \r\nobserved 00005555.00005555 \r\nxor 55550000.55550000 \r\n3,0>; \r\n*** Aborting Test List due to severe error *** \r\n\r\n应该是CPU有问题了。