关于dma_alloc_coherent函数

xiaojsj

ldd3上说，dma_alloc_coherent函数分配的内存是一致性DMA映射的，
就是说cpu和dma看到的内存内容是一致的。如果要做到cpu和dma看到内容是一致的，那就是说，
这段内存必须是不经过cache的。

我在看代码的时候，在分配内存时，使用了如下的内存分配标志。
#define pgprot_dmacoherent(prot) \
        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
即指明该内存是L_PTE_MT_BUFFERABLE的，这是什么意思，我的理解，应该设置为：L_PTE_MT_UNCACHED才合理吧？

L_PTE_MT_BUFFERABLE和L_PTE_MT_UNCACHED有什么区别呢？

xiaojsj

顶下，直到的回复下，大牛们！！！

瀚海书香

回复 1# xiaojsj

ldd3上说，dma_alloc_coherent函数分配的内存是一致性DMA映射的，
就是说cpu和dma看到的内存内容是一致的。如果要做到cpu和dma看到内容是一致的，那就是说，
这段内存必须是不经过cache的。

我在看代码的时候，在分配内存时，使用了如下的内存分配标志。
#define pgprot_dmacoherent(prot) \
        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
即指明该内存是L_PTE_MT_BUFFERABLE的，这是什么意思，我的理解，应该设置为：L_PTE_MT_UNCACHED才合理吧？

L_PTE_MT_BUFFERABLE和L_PTE_MT_UNCACHED有什么区别呢？

没有好好看代码吧，这里是有#ifdef的

1. #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
   
2. #define pgprot_dmacoherent(prot) \
   
3.         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
   
4. #define __HAVE_PHYS_MEM_ACCESS_PROT
   
5. struct file;
   
6. extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
   
7.                                      unsigned long size, pgprot_t vma_prot);
   
8. #else
   
9. #define pgprot_dmacoherent(prot) \
   
10.         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
    
11. #endif

复制代码

只有在DMA bufferable的情况下，才会只关闭cache而开启write buffer；否则会关闭cache和write buffer.

另外关于cache和write buffer可以看一下这个博文http://blog.chinaunix.net/uid-20662820-id-3917558.html

   

arm-linux-gcc

cache有cacheable和bufferable两个属性
L_PTE_MT_UNCACHED是同时关掉了cacheable和bufferable
L_PTE_MT_BUFFERABLE只是关掉了cacheable

cortex-a9的都是默认打开了CONFIG_ARM_DMA_MEM_BUFFERABLE的


config ARM_DMA_MEM_BUFFERABLE
        bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
        depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
                     MACH_REALVIEW_PB11MP)
        default y if CPU_V6 || CPU_V6K || CPU_V7
        help
          Historically, the kernel has used strongly ordered mappings to
          provide DMA coherent memory.  With the advent of ARMv7, mapping
          memory with differing types results in unpredictable behaviour,
          so on these CPUs, this option is forced on.

          Multiple mappings with differing attributes is also unpredictable
          on ARMv6 CPUs, but since they do not have aggressive speculative
          prefetch, no harm appears to occur.

          However, drivers may be missing the necessary barriers for ARMv6,
          and therefore turning this on may result in unpredictable driver
          behaviour.  Therefore, we offer this as an option.

          You are recommended say 'Y' here and debug any affected drivers.







看看有关cache原理的文章就知道了，一搜一大把

xiaojsj

我拜读兄台的文章：有如下疑问需要请教下:
       a:在有write buffer的情况，如果新的更新的数据已经放在write buffer中了，这个时候cpu继续执行，但在继续执行的过程，由于要去读这个刚更新的，还在write buffer中的内容，会发生什么情况。
       b：write can not be externally aborted，是什么意思呢？
      
谢谢各位都来赐教啊！！！！

回复 3# 瀚海书香


   

瀚海书香

回复 5# xiaojsj
In addition to the MMU-generated aborts, ARM810 has an external abort pin which may be
used to flag an error on an external memory access. However, not all accesses can be aborted
in this way, so this pin must be used with great care. The following section describes the
restrictions.
The following accesses may be aborted and restarted safely. In the case of a read-lock-write
sequence in which the read aborts, the write will not happen.
Reads
Unbuffered writes
Level One descriptor fetch
Level Two descriptor fetch
read-lock-write sequence
Cacheable reads (linefetches)
A linefetch may be safely aborted on any word in the transfer. If an abort occurs during the
linefetch then the cache line will be invalidated. If the abort happens on a word that has been
requested by the ARM8, the instruction will be aborted, otherwise the cache line will be
invalidated but program flow will not be interrupted. The line is therefore invalidated under all
circumstances.
Buffered writes.
Buffered writes cannot be externally aborted. Therefore, the system should be configured such
that it does not do buffered writes to areas of memory which are capable of flagging an external
abort.
Writes to Cacheable Regions
Writes to cacheable regions and cache write-backs are performed as buffered writes and
cannot be externally aborted. The system design should ensure that writes to cacheable
regions are not externally aborted.

   

瀚海书香

回复 5# xiaojsj
具体可以看看这个http://stuff.mit.edu/afs/sipb/co ... /arm/ARM810vE_3.pdf