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本帖最后由 asuka2001 于 2014-04-23 15:16 编辑
回复 14# l4rmbr
1)恩,我是确认 DEC alpha同样保证有数据依赖的内存读取的顺序性。即不论预读与否,总是先 LOAD p;然后再 LOAD p->a。
至于 DEC alpha需要 data dependency barrier的原因 Documentation/memory-barrier.txt里写的很清楚:
[!] Note that this extremely counterintuitive situation arises most easily on
machines with split caches, so that, for example, one cache bank processes
even-numbered cache lines and the other bank processes odd-numbered cache
lines. The pointer P might be stored in an odd-numbered cache line, and the
variable B might be stored in an even-numbered cache line. Then, if the
even-numbered bank of the reading CPU's cache is extremely busy while the
odd-numbered bank is idle, one can see the new value of the pointer P (&B),
but the old value of the variable B (2).
2) 我想说明的是需要 data dependency barrier的原因不在于预读!而是 split cache的更新顺序与写者的实际 store顺序不一致!
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