ultra60 开机无法启动 (续)

zichen1918

五一期间我好好拆卸了一下老爷机，我去掉一颗cpu，之前的错误log没有再出现：
0> <00> Memory Stack Test           
0>      ERROR: CPU Slave 2 Timeout
0>      WARNING: Unable to dispatch Int to mid 00000002
0>      WARNING: Unable to dispatch Int to mid 00000002
0>      WARNING: Unable to dispatch Int to mid 00000002

我又调整两颗cpu的顺序，错误log再次出现，我觉得很可能是主板cpu的槽位那里出了问题；

对于内存相关的异常log，我将16根内存重新分组插了一遍，发现有一组内存报错，具体哪根不能确定，没办法，拆了这组，内存报错也没再出现：
0>      Unexpected event occurred - Trap
2> <00> DMMU TLB Tag Access Test        
0>      tl  tt  tstate             tpc                tnpc
0>      01  30  00000099.80001604  ffffffff.f00b0b98  ffffffff.f00b0b9c
0>      DMMU SFSR 00000000.0058043f                                    
0>      DMMU SFAR 00000000.00000000
0>      (FV)  Fault Valid Bit Set  
0>      (OW)  Overwrite Bit Set  
0>      (ASI) 0x58            
0>      (FT)  Ill LDA/STA ASI, VA, RW size
0>      (CT)  Context 3                  
0>      (PR)  Privilege Bit Set
0>      (W)   Write Bit Set   
0>      AFSR 00000000.00100000
0>      AFAR 00000000.08560000
0>      (CE)   Correctable ECC Error
0>      SDBH = 00000000.000001f1 SDBL = 00000000.00000031
0>                                                      
        Failing address in SIMM Pair 0, SIMM 0

目前最新log如下：
Hardware Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000
tton Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

Probing keyboard Done
%o0 = 0000.0000.0054.4001

Executing Power On SelfTest

0>
0>@(#) Sun Ultra 60(UltraSPARC-II 2-way) UPA/PCI POST 2.0.2 10/19/1998 10:46 AM
0>INFO: Processor 0 is master.                                                
0>                           
0> <00> Init System BSS
0> <00> NVRAM Battery Detect Test
0>STATUS =FAILED                 
0>TEST   =NVRAM Battery Detect
TTF    =0                     
PASSES =1
ERRORS =1
SUSPECT=NVRAM U2706
0>MESSAGE=NVRAM Low Battery
        addr 000001ff.f1001ff0
        exp  00               
        obs  10
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> IMMU TLB Tag Access Test
0> <00> IMMU TLB RAM Access Test
0> <00> Probe Ecache            
0>INFO: CPU 450 MHz: 4096KB Ecache
0> <00> Ecache RAM Addr Test      
0> <00> Ecache Tag Addr Test
0> <00> Ecache Tag Test     
0> <00> Invalidate Ecache Tags
0>INFO: Processor 2 - UltraSPARC-II.
0> <00> Init SC Regs               
0> <00> SC Address Reg Test
0> <00> SC Reg Index Test  
0> <00> SC Regs Test     
0> <00> SC Dtag RAM Addr Test
0> <00> SC Cache Size Init   
0> <00> SC Dtag RAM Data Test
0> <00> SC Dtag Init         
0> <00> Probe Memory
0>INFO: 512MB Bank 0
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Malloc Post Memory
0> <00> Init Post Memory  
0> <00> Post Memory Addr Test
0> <00> Map PROM/STACK/NVRAM in DMMU
0> <00> Memory Stack Test           
0>      ERROR: CPU Slave 2 Timeout
0>      WARNING: Unable to dispatch Int to mid 00000002
0>      WARNING: Unable to dispatch Int to mid 00000002
0>      WARNING: Unable to dispatch Int to mid 00000002
0> <00> DMMU Hit/Miss Test                             
0> <00> IMMU Hit/Miss Test
0> <00> DMMU Little Endian Test
0> <00> IU ASI Access Test     
0> <00> FPU ASI Access Test
0> <1f> Init Psycho        
0> <1f> PIO Read Error, Master **rt Test
0> <1f> PIO Read Error, Target **rt Test
0> <1f> PIO Write Error, Master **rt Test
0> <1f> PIO Write Error, Target **rt Test
0> <1f> Timer Increment Test              
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> Init Memory      
0> <00> Memory Addr w/ Ecache Test
0>INFO: 512MB Bank 0              
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Addr Test
0>INFO: 512MB Bank 0         
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Memory Addr Test
0>INFO: 512MB Bank 0        
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory Status Test
0>INFO: 512MB Bank 0      
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test               
0> <00> CPU Softint Reg and Int Test
0> <1f> Init Psycho                 
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
0> <1f> Psycho Perf Cntl Reg Test     
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test   
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test            
0> <1f> Timer Periodic Test
0> <1f> Mondo Int Map (short) Reg Test
0> <1f> Mondo Int Set/Clr Reg Test   
0> <1f> Psycho IOMMU Regs Test   
0> <1f> Psycho IOMMU RAM Address Test
0> <1f> Psycho IOMMU CAM Address Test
0> <1f> IOMMU TLB Compare Test      
0> <1f> IOMMU TLB Flush Test  
0> <1f> Stream Buff A Control Reg Test
0> <1f> Psycho ScacheA Page Tag Addr Test
0> <1f> Psycho ScacheA Line Tag Addr Test
0> <1f> Psycho ScacheA RAM Addr Test     
0> <1f> Psycho ScacheA Error Status NTA Test
0> <1f> Psycho ScacheB Page Tag Addr Test   
0> <1f> Psycho ScacheB Line Tag Addr Test
0> <1f> Psycho ScacheB RAM Addr Test     
0> <1f> Psycho ScacheB Error Status NTA Test
0> <1f> PBMA PCI Config Space Regs Test     
0> <1f> PBMA Control/Status Reg Test   
0> <1f> PBMA Diag Reg Test         
0> <1f> PBMB PCI Config Space Regs Test
0> <1f> PBMB Control/Status Reg Test   
0> <1f> PBMB Diag Reg Test         
0> <00> FPU Regs Test     
0> <00> FPU Move Regs Test
0> <00> FPU State Reg Test
0> <00> FPU Functional Test
0> <00> FPU Trap Test      
0> <00> DMMU Primary Context Reg Test
0> <00> DMMU Secondary Context Reg Test
0> <00> DMMU TSB Reg Test              
0> <00> DMMU Tag Access Reg Test
0> <00> DMMU VA Watchpoint Reg Test
0> <00> DMMU PA Watchpoint Reg Test
0> <00> IMMU TSB Reg Test         
0> <00> IMMU Tag Access Reg Test
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> Dcache RAM Test         
0> <00> Dcache Tag Test
0> <00> Icache RAM Test
0> <00> Icache Tag Test
0> <00> Icache Next Test
0> <00> Icache Predecode Test
0> <00> CPU Addr Align Trap Test
0> <00> DMMU Access Priv Page Test
0> <00> DMMU Write Protected Page Test
0> <1f> Init Psycho                  
0> <1f> Pri CE ECC Error Test
0> <1f> Pri UE ECC Error Test
0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
0> <1f> Pri 3 bit UE ECC Err Test            
0> <1f> Streaming DMA UE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA UE ECC Rd Error Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA CE ECC Rd Err Ebus Test   
0> <1f> Consistent DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA CE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA Wr Data Parity Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Ebus Test      
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Ebus Test   
0> <1f> Pass-Thru DMA CE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA Write Data Parity Err, Lpbk Test
0> <1f> Init Psycho                                   
0> <1f> Mondo Generate Interrupt Test
0> <1f> Timer Interrupt Test         
0> <1f> Timer Interrupt w/ periodic Test
0> <1f> Psycho Stream Buff A Flush Sync Test
0> <1f> Psycho Stream Buff B Flush Sync Test
0> <1f> Psycho Stream Buff A Flush Invalidate Test
0> <1f> Psycho Stream Buff B Flush Invalidate Test
0> <1f> Psycho Merge Buffer w/ Scache A Test      
0> <1f> Psycho Merge Buffer w/ Scache B Test
0> <1f> Consist DMA Rd, IOMMU miss Ebus Test
0> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
0> <1f> Consist DMA Rd, IOMMU hit Ebus Test
0> <1f> Consist DMA Rd, IOMMU hit Lpbk Test
0> <1f> Consist DMA Wr, IOMMU miss Ebus Test
0> <1f> Consist DMA Wr, IOMMU miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU hit Ebus Test
0> <1f> Consist DMA Wr, IOMMU hit Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit Ebus Test           
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit(prev wr) Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit(prev wr) Ebus Test  
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Ebus Test        
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Lpbk Test
0> <1f> Pass-Thru DMA Rd, Ebus device Test                     
0> <1f> Pass-Thru DMA Rd, Loopback Mode Test
0> <1f> Pass-Thru DMA Wr, Ebus device Test  
0> <1f> Pass-Thru DMA Wr, Loopback Mode Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Ebus Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache LRU Lock Ebus Test   
0> <1f> Stream DMA Rd, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU LRU Locked Ebus Test         
0> <1f> Consist DMA Wr, IOMMU LRU Lock Lpbk Test  
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Ebus Test   
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Lpbk Test
0> <00> Init Memory                                                
0>INFO: 512MB Bank 0
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory w/ Ecache Test
0>INFO: 512MB Bank 0         
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Test
0>INFO: 512MB Bank 0     
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Blk Memory Test
0>INFO: 512MB Bank 0      
0>INFO:   0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00> Test 0: prefetch_mr                    
0> <00> Test 1: prefetch to non-cacheable page
0> <00> Test 2: prefetch to page with dmmu misss
0> <00> Test 3: prefetch miss does not check alignment
0> <00> Test 4: prefetcha with asi 0x4c is noped      
0> <00> Test 5: prefetcha with asi 0x54 is noped
0> <00> Test 6: prefetcha with asi 0x6e is noped
0> <00> Test 7: prefetcha with asi 0x76 is noped
0> <00> Test 8: prefetch with fcn 5            
0> <00> Test 9: prefetch with fcn 2
0> <00> Test 10: prefetch with fcn 12
0> <00> Test 11: prefetch with fcn 16 is noped
0> <00> Test 12: prefetch with fcn 29 is noped
0> <00> Test 13: prefetcha with asi 0x15 is noped
0> <00> Test 14: prefetch with fcn 3            
0> <00> Test 15: prefetcha14 with fcn 2
0> <00> Test 16: prefetcha80_mr        
0> <00> Test 17: prefetcha81_1r
0> <00> Test 18: prefetcha10_mw
0> <00> Test 19: prefetcha80_17 is noped
0> <00> Test 20: prefetcha10_6: illegal instruction trap
0> <00> Test 21: prefetcha11_1w                        
0> <00> Test 22: prefetcha81_31
0> <00> Test 23: prefetcha11_15: illegal instruction trap
0>STATUS =FAILED  :  First failing device is NVRAM U2706.


Power On Selftest Completed
    Status  = 0000.0000.0000.0001 ffff.ffff.f00b.3818 ff9d.ffff.0bd1.e111
ftware Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

@(#) UPA/PCI 3.23 Version 1 created 1999/07/16 12:08
Clearing DTAGS  Done
Probing Memory Done
MEM BASE = 0000.0000.a000.0000
MEM SIZE = 0000.0000.2000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2800
PC = 0000.0000.0000.2844
Decompressing into Memory Done
Size = 0000.0000.0006.eb80
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1   0   0   0   0 :   0 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: drive detected on ID0
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 SUNW,ffb
Probing /pci@1f,4000 at Device 1  pci108e,1000 network
Probing /pci@1f,4000 at Device 3  scsi disk tape scsi disk tape
Probing /pci@1f,4000 at Device 2  Nothing there
Probing /pci@1f,4000 at Device 4  Nothing there
Probing /pci@1f,4000 at Device 5  Nothing there
Probing /pci@1f,2000 at Device 1  Nothing there
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1   0   0   0   0 :   0 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: drive detected on ID0
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 SUNW,ffb
Probing /pci@1f,4000 at Device 1  pci108e,1000 network
Probing /pci@1f,4000 at Device 3  scsi disk tape scsi disk tape
Probing /pci@1f,4000 at Device 2  Nothing there
Probing /pci@1f,4000 at Device 4  Nothing there
Probing /pci@1f,4000 at Device 5  Nothing there
Probing /pci@1f,2000 at Device 1  Nothing there

(2 X UltraSPARC-II 450MHz), No Keyboard
OpenBoot 3.23, 1536 MB memory installed, Serial #15728639.
Ethernet address ff:ef:ff:ff:ff:ef, Host ID: ffefffff.


The IDPROM contents are invalid

Power On Self Test Failed.  Cause: NVRAM U2706                        
{0} ok

cpu报错是因为我又插上了第二颗cpu；我尝试在ok模式下通过boot disk启动系统，
Boot device: /***@1f,4000/***@3/***@1,0 File and args: 停留在这里很久没变化

不知道该怎么办了......

zichen1918

今天一直查sun ultra60手册，根据日志信息，NVRAM可能是没电了，需要更换；看到网上有信息说可以再编程，不知道可不可行；有没有人遇到此类问题呢？

nimysun

回复 2# zichen1918

  这个工作站确实够老的，很多人估计都把相关的技术都给忘掉了。
  能给到您的建议就是用最小化CPU内存的硬件配置测试一下所有的CPU和内存是否都正常工作。
另，nvram是存储bios的配置的，所以主板电池没有电的话，是不会影响系统启动的。
  我觉得您是多个问题在这里。

  首先是主板内存CPU可能存在硬件问题，注意那个u2706，我不知道是否是指的是一个内存插槽，或者内存。

  第二个是硬盘启动问题，我觉得这个是你的硬盘本身的问题，建议从其他硬盘或者光驱引导一下。看看这个硬盘是否有问题。

  此外这个版真是萧条了，难得有新帖子。

zichen1918

好，收到，我之前经常看到东方蜘蛛，现在都看不到了；
上次搬家，嫌机器太重，就用拉车走了前后单元楼的距离，可能给颠簸坏了；
我五一期间进行的测试，内存之前是2G，拆到一组，目前1.5G，已经看不到内存报错了；两颗cpu都切换过槽位，只有一个槽位可以启动系统；我不确认u60是否第二个cpu槽位能单独启动；
u2706 我查过u60的手册，这是nvram那个芯片，芯片背面写的是u2706；我觉得你说的硬盘启动问题有道理，估计硬盘也出问题了，我周末用光盘启动一下试试；这个家搬的好心疼。

zichen1918

换下来的四根内存，金手指部分有一些白色污渍，用橡皮擦不下来，可能时间太久，我想找时间用牙签逐一清理一下再试试；一直觉得内存挺皮实的，没想到禁不住轻微的颠簸

zichen1918

今天为啥发了三贴，只能看到其中的一个

lining0925

我有HOSTID卖

lining0925

如果你可以提供你之前的MAC地址给我，也可以帮你改跟你之前一样

lining0925

haishui

可以进入修复模式