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V480无法启动 [复制链接]

baonan97

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发表于 2008-04-02 18:59 |只看该作者 |倒序浏览
V480系统无法启动,无法进入OK状态.
下面是诊断模式的信息,清高手指点问题原因
@(#)OBP 4.13.0 2004/01/19 18:26 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online: CPU0 CPU1 CPU2 CPU3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done

Probing Centerplane....part# 501-6790-01 serial# 001149
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 060958
Probing System RSC.....part# 501-5856-06 serial# 242950
Probing PwrDistBoard...part# 375-3006-05 serial# M68950
Probing PowerSupply0...part# 300-1480-05 serial# N25536
Probing PowerSupply1...part# 300-1480-05 serial# N25403
Probing FCAL BPlane0...part# 501-5822-04 serial# 061034
Probing GPTwo Slot A...part# 501-6707-01 serial# 004510
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  CPU rated speed 1050MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...part# 501-6707-01 serial# 004673
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  CPU rated speed 1050MHz; ECache 8MB 3.3ns

Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU0 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU1 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU2 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU3 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00 Done
Setting system speed (and resetting)...
<*>
Set Speed Reset

@(#)OBP 4.13.0 2004/01/19 18:26 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.2042
0:0>
0:0>@(#) Sun Fire[TM] V480 POST 4.13.0 2004/02/12 19:17
       /export/common-source/firmware_re/post/post-build-4.13.0/Camelot/cstone/integrated  (firmware_re)
0:0>Copyright ?2004 Sun Microsystems, Inc. All rights reserved
  SUN PROPRIETARY/CONFIDENTIAL.
  Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>Keyswitch in DIAGNOSTIC POSITION.
0:0>Diag level set to MIN.
0:0>Verbosity level set to 0.
0:0>MFG scrpt mode set NORM
0:0>I/O port set to serial TTYA.
0:0>
0:0>Start selftest...
0:0>CPUs present in system: 0:0 1:0 2:0 3:0
0:0>Test CPU(s).....
0:0>Init CPU
0:0>    UltraSparc_III_plus Version 11.1
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>Probe Ecache
0:0>    Size = 00000000.00800000...
0:0>Ecache Data Bitwalk
0:0>Ecache Address Bitwalk
0:0>Scrub and Setup Ecache
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
1:0>Init CPU
2:0>Init CPU
3:0>Init CPU
1:0>    UltraSparc_III_plus Version 11.1
2:0>    UltraSparc_III_plus Version 11.1
3:0>    UltraSparc_III_plus Version 11.1
1:0>DMMU Registers Access
2:0>DMMU Registers Access
3:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
2:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
2:0>DMMU TLB TAGS Access
3:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
2:0>IMMU Registers Access
3:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
2:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
2:0>IMMU TLB TAGS Access
3:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0>    Size = 00000000.00800000...
2:0>Probe Ecache
2:0>    Size = 00000000.00800000...
3:0>Probe Ecache
3:0>    Size = 00000000.00800000...
1:0>Ecache Data Bitwalk
2:0>Ecache Data Bitwalk
3:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
2:0>Ecache Address Bitwalk
3:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
2:0>Scrub and Setup Ecache
3:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
2:0>Setup and Enable DMMU
3:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
2:0>Setup DMMU Miss Handler
3:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
2:0>Test and Init Temp Mailbox
3:0>Test and Init Temp Mailbox
0:0>Init Scan/I2C.....
0:0>Initializing Scan Database
0:0>Mask DAR errors off
0:0>Init CDX DTL
0:0>Init DAR DTL
0:0>Enable Partial DAR error
0:0>Init DCS DTL
0:0>Init I2C
0:0>Unquiesce Safari
0:0>Margin all voltages to nominal
0:0>Scan ring integrity
0:0>Set Trip Temp CPU 0 to 110C
0:0>Set Trip Temp CPU 1 to 110C
0:0>Set Trip Temp CPU 2 to 110C
0:0>Set Trip Temp CPU 3 to 110C
0:0>MON MAR  31 11:15:35 GMT 8
0:0>Safari quick check
0:0>     to IO-bridge_0
0:0>     to IO-bridge_1
0:0>Safari full  check
0:0>     to IO-bridge_0
0:0>     to IO-bridge_1
0:0>Disable CPU 0 error checking
0:0>Disable CPU 1 error checking
0:0>Disable CPU 2 error checking
0:0>Disable CPU 3 error checking
0:0>Basic Memory Test.....
0:0>Probe and Setup Memory
0:0>INFO:          512MB Bank 0
0:0>INFO:          512MB Bank 1
0:0>INFO:          512MB Bank 2
0:0>INFO:          512MB Bank 3
0:0>
0:0>Data Bitwalk on Master
0:0>    Test Bank 0.
0:0>    Test Bank 1.
0:0>    Test Bank 2.
0:0>    Test Bank 3.
0:0>Address Bitwalk on Master
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 0: 00000000.00000000 to 00000000.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 1: 00000001.00000000 to 00000001.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 2: 00000002.00000000 to 00000002.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 3: 00000003.00000000 to 00000003.20000000.
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is 7423.
0:0>The Memory's Content Size value is a0784.
0:0>Success...  Checksum on Memory Validated.
1:0>Safari quick check
1:0>     to IO-bridge_0
1:0>     to IO-bridge_1
1:0>Safari full  check
1:0>     to IO-bridge_0
1:0>     to IO-bridge_1
2:0>Safari quick check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
2:0>Safari full  check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
3:0>Safari quick check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
3:0>Safari full  check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
1:0>Probe and Setup Memory
2:0>Probe and Setup Memory
3:0>Probe and Setup Memory
1:0>INFO:          512MB Bank 0
1:0>INFO:          512MB Bank 1
1:0>INFO:          512MB Bank 2
1:0>INFO:          512MB Bank 3
1:0>
2:0>INFO:          512MB Bank 0
2:0>INFO:          512MB Bank 1
2:0>INFO:          512MB Bank 2
2:0>INFO:          512MB Bank 3
2:0>
3:0>INFO:          512MB Bank 0
3:0>INFO:          512MB Bank 1
3:0>INFO:          512MB Bank 2
3:0>INFO:          512MB Bank 3
3:0>
1:0>Set Mailbox
2:0>Set Mailbox
3:0>Set Mailbox
0:0>Data Bitwalk on Slave 1
0:0>    Test Bank 0.
0:0>    Test Bank 1.
0:0>    Test Bank 2.
0:0>    Test Bank 3.
0:0>Data Bitwalk on Slave 2
0:0>    Test Bank 0.
0:0>    Test Bank 1.
0:0>    Test Bank 2.
0:0>    Test Bank 3.
0:0>Data Bitwalk on Slave 3
0:0>    Test Bank 0.
0:0>    Test Bank 1.
0:0>    Test Bank 2.
0:0>    Test Bank 3.
0:0>Address Bitwalk on Slave 1
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 0: 00000010.00000000 to 00000010.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 1: 00000011.00000000 to 00000011.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 2: 00000012.00000000 to 00000012.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 1:0 Bank 3: 00000013.00000000 to 00000013.20000000.
0:0>Address Bitwalk on Slave 2
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 0: 00000020.00000000 to 00000020.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 1: 00000021.00000000 to 00000021.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 2: 00000022.00000000 to 00000022.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 3: 00000023.00000000 to 00000023.20000000.
0:0>Address Bitwalk on Slave 3
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 0: 00000030.00000000 to 00000030.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 1: 00000031.00000000 to 00000031.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 2: 00000032.00000000 to 00000032.20000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 3:0 Bank 3: 00000033.00000000 to 00000033.20000000.
1:0>Setup Final DMMU Entries
2:0>Setup Final DMMU Entries
3:0>Setup Final DMMU Entries
1:0>Map Slave POST to master memory
2:0>Map Slave POST to master memory
3:0>Map Slave POST to master memory
1:0>Print Mem Config
1:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1:0>Memory in non-interleave config:
1:0>    Bank 0    512MB : 00000010.00000000 -> 00000010.20000000.
1:0>    Bank 1    512MB : 00000011.00000000 -> 00000011.20000000.
1:0>    Bank 2    512MB : 00000012.00000000 -> 00000012.20000000.
1:0>    Bank 3    512MB : 00000013.00000000 -> 00000013.20000000.
2:0>Print Mem Config
2:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:0>Memory in non-interleave config:
2:0>    Bank 0    512MB : 00000020.00000000 -> 00000020.20000000.
2:0>    Bank 1    512MB : 00000021.00000000 -> 00000021.20000000.
2:0>    Bank 2    512MB : 00000022.00000000 -> 00000022.20000000.
2:0>    Bank 3    512MB : 00000023.00000000 -> 00000023.20000000.
3:0>Print Mem Config
3:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3:0>Memory in non-interleave config:
3:0>    Bank 0    512MB : 00000030.00000000 -> 00000030.20000000.
3:0>    Bank 1    512MB : 00000031.00000000 -> 00000031.20000000.
3:0>    Bank 2    512MB : 00000032.00000000 -> 00000032.20000000.
3:0>    Bank 3    512MB : 00000033.00000000 -> 00000033.20000000.
0:0>Memory Block.....
1:0>Scrub Memory
2:0>Scrub Memory
3:0>Scrub Memory
0:0>Print Mem Config
0:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:0>Memory in non-interleave config:
0:0>    Bank 0    512MB : 00000000.00000000 -> 00000000.20000000.
0:0>    Bank 1    512MB : 00000001.00000000 -> 00000001.20000000.
0:0>    Bank 2    512MB : 00000002.00000000 -> 00000002.20000000.
0:0>    Bank 3    512MB : 00000003.00000000 -> 00000003.20000000.
0:0>Scrub Memory
1:0>Quick Block Mem Test
2:0>Quick Block Mem Test
3:0>Quick Block Mem Test
1:0>Quick Test 16777216 bytes at 00000010.00000000
2:0>Quick Test 16777216 bytes at 00000020.00000000
3:0>Quick Test 16777216 bytes at 00000030.00000000
0:0>Quick Block Mem Test
0:0>Quick Test 16777216 bytes at 00000000.00600000
0:0>40% Done...
1:0>Flush Caches
2:0>Flush Caches
3:0>Flush Caches
0:0>Flush Caches
1:0>Get code in ecache.
2:0>Get code in ecache.
3:0>Get code in ecache.
0:0>Get code in ecache.
0:0>IO-Bridge Tests.....
0:0>IO-Bridge unit 0 init      test
0:0>IO-Bridge unit 1 init      test
0:0>IO-Bridge unit 0 reg       test
0:0>IO-Bridge unit 0 mem       test
0:0>IO-Bridge unit 0 PCI DMA A test
0:0>IO-Bridge unit 0 PCI DMA B test
0:0>IO-Bridge unit 0 PCI merg  test
0:0>IO-Bridge unit 0 PCI iommu test
0:0>IO-Bridge unit 0 PCI stc   test
0:0>IO-Bridge unit 0 interrupt test
0:0>IO-Bridge unit 1 reg       test
0:0>IO-Bridge unit 1 mem       test
0:0>IO-Bridge unit 1 PCI DMA C test
0:0>IO-Bridge unit 1 PCI DMA D test
0:0>IO-Bridge unit 1 PCI merg  test
0:0>IO-Bridge unit 1 PCI iommu test
0:0>IO-Bridge unit 1 PCI stc   test
0:0>IO-Bridge unit 1 interrupt test
1:0>IO-Bridge unit 0 init      test
1:0>IO-Bridge unit 0 PCI merg  test
1:0>IO-Bridge unit 0 interrupt test
1:0>IO-Bridge unit 1 init      test
1:0>IO-Bridge unit 1 PCI merg  test
1:0>IO-Bridge unit 1 interrupt test
2:0>IO-Bridge unit 0 init      test
2:0>IO-Bridge unit 0 PCI merg  test
2:0>IO-Bridge unit 0 interrupt test
2:0>IO-Bridge unit 1 init      test
2:0>IO-Bridge unit 1 PCI merg  test
2:0>IO-Bridge unit 1 interrupt test
3:0>IO-Bridge unit 0 init      test
3:0>IO-Bridge unit 0 PCI merg  test
3:0>IO-Bridge unit 0 interrupt test
3:0>IO-Bridge unit 1 init      test
3:0>IO-Bridge unit 1 PCI merg  test
3:0>IO-Bridge unit 1 interrupt test
1:0>FPU Registers and Data Path
2:0>FPU Registers and Data Path
3:0>FPU Registers and Data Path
0:0>FPU Registers and Data Path
1:0>FPU Move Registers
2:0>FPU Move Registers
3:0>FPU Move Registers
0:0>FPU Move Registers
1:0>FSR Read/Write
2:0>FSR Read/Write
3:0>FSR Read/Write
0:0>FSR Read/Write
1:0>FPU BLOCK REG TEST
2:0>FPU BLOCK REG TEST
3:0>FPU BLOCK REG TEST
0:0>FPU BLOCK REG TEST
0:0>
0:0>Motherboard/Centerplane Board Part Number:
0:0>    5016790-01-04
0:0>IO/Riser Board Part Number:
0:0>    5015820-04-58
0:0>CPUA Board Part Number:
0:0>    5016707-01-52
0:0>CPUB Board Part Number:
0:0>    5016707-01-52
0:0>Enable Errors.....
0:0>Turn IO-Bridge 0 errors on
0:0>Turn IO-Bridge 1 errors on
0:0>Turn CPU 0 errors on
0:0>Turn CPU 1 errors on
0:0>Turn CPU 2 errors on
0:0>Turn CPU 3 errors on
0:0>Turn Module A DCDS errors on
0:0>Turn Module B DCDS errors on
0:0>Turn DCS errors on
0:0>Turn DAR errors on
0:0>Turn error traps on
0:0>INFO:
0:0>    POST Passed all devices.
0:0>POST:       Return to OBP.


CPU0: System Power On Selftest Completed
    Pass/Fail Status  = 0000.0000.0000.0000
    ESB Overall Status  = ffff.ffff.ffff.ffff


<*>
POST Reset

@(#)OBP 4.13.0 2004/01/19 18:26 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Configuring CPUs..........
... CPU0 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU1 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU2 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU3 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00 Done
<*>
CPU Configuration Reset

@(#)OBP 4.13.0 2004/01/19 18:26 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Enabling Safari .......... CPU0 CPU1 CPU2 CPU3 Done
Probing Memory............
Probing CPU0 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# 49EECE,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# 49F42B,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# 49EE1A,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# 49EDA7,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# 49F487,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# 49F460,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# 49EDA4,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# 49ED29,  128MB + 128MB,  SC#0
Probing CPU1 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# 49ED9B,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# 49ED32,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# 49ED34,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# 49ED2F,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# 49F45C,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# 49F26A,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# 49ED0E,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# 49ED9E,  128MB + 128MB,  SC#0
Probing CPU2 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# 49EE43,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# 49EDA2,  128MB + 128MB,  SC#0
Mungeing Memory...........Done
HiMem: 0000.00b0.0000.0000, size: 0000.0001.0000.0000
Configuring Memory........ CPU0 CPU1 CPU2 CPU3 Done
Init ICache/etc........... CPU0 CPU1 CPU2 CPU3 Done
Init ECache Tags.......... CPU0 CPU1 CPU2 CPU3 Done
Clearing TLBs............. CPU0 CPU1 CPU2 CPU3 Done
Setup I/DTLBs............. CPU0 CPU1 CPU2 CPU3 Done
Enabling Cache/MMUs....... CPU0 CPU1 CPU2 CPU3 Done
Init ECache Data.......... CPU0 CPU1 CPU2 CPU3 Done
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 96KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.ae4f.eb3c;  ROM CRC = 0000.0000.ae4f.eb3c
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.0290 (449KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0
Boot  CPU3 starting Forth at 0000.0000.f000.00e0

ttya initialized
Probing gptwo at 0,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 1,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 2,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 3,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 4,0 Nothing there
Probing gptwo at 5,0 Nothing there
Probing gptwo at 6,0 Nothing there
Probing gptwo at 7,0 Nothing there
Probing gptwo at 8,0 pci pci
Probing gptwo at 9,0 pci pci
Loading Support Packages: obp-tftp kbd-translator SUNW,i2c-ram-device
   SUNW,fru-device
Loading onboard drivers: ebus flashprom bbc power i2c fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru nvram idprom fru
   fru i2c temperature temperature temperature ioexp ioexp ioexp
   temperature ioexp ioexp ioexp ioexp temperature-sensor fru fru fru
   fru fru rscrtc rtc gpio pmc rsc-control rsc-console serial
Memory Configuration:
CPU0 Bank0  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #0
CPU0 Bank1  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #2
CPU0 Bank2  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #4
CPU0 Bank3  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #6
CPU1 Bank0  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #0
CPU1 Bank1  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #2
CPU1 Bank2  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #4
CPU1 Bank3  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #6
CPU2 Bank0  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #1
CPU2 Bank1  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #3
CPU2 Bank2  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #5
CPU2 Bank3  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #7
CPU3 Bank0  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #1
CPU3 Bank1  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #3
CPU3 Bank2  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #5
CPU3 Bank3  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #7
Probing /pci@8,600000 Device 1  pci
........
ilinch

论坛徽章:
0
2楼 [报告]
发表于 2008-04-03 00:48 |只看该作者
你的意思是无法用stop-a到ok下面?
是不是你的钥匙一直在诊断模式下面啊 调到nomal下再试试
还有 你接显示器了吗?有反应吗?
实战分享：从技术角度谈机器学习入门| 【大话IT】RadonDB低门槛向MySQL集群下战书 | ChinaUnix打赏功能已上线！ | 新一代分布式关系型数据库RadonDB知多少？
xiazhen9842

论坛徽章:
0
3楼 [报告]
发表于 2008-04-03 09:18 |只看该作者
我总感觉你没有把所有的错误信息全贴出来啊.从这上面看硬件也没有什么错.
实战分享：从技术角度谈机器学习入门| 【大话IT】RadonDB低门槛向MySQL集群下战书 | ChinaUnix打赏功能已上线！ | 新一代分布式关系型数据库RadonDB知多少？
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