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本帖最后由 cjaizss 于 2010-12-30 08:47 编辑
哦,看明白你的波形图了,这个好办了
cjaizss 发表于 2010-12-29 16:49 ![]()
module cnt_module(clk,nrst,A,B,C,count);
input clk,nrst,A,B,C;
output [31:0]count;
reg A1,A2,B1,B2,Ar,Br;
reg [31:0]count;
always@(negedge nrst or posedge clk)
if(!nrst)
{A1,A2,B1,B2}<=4'b1111;
else
{A1,A2,B1,B2}<={A,A1,B,B1};
always@(negedge nrst or posedge clk)
if(!nrst)
{Ar,Br}<=2'b00;
else begin
if(A1==A2)
Ar<=A1;
if(B1==B2)
Br<=B1;
end
wire A_posedge=A1==A2&&A2!=Ar;
always@(negedge nrst or posedge clk)
if(!nrst)
count <=0;
else
begin
if(A_posedge)
begin
if(Br)
count<=count-1;
else
count<=count+1;
end
end
endmodule |
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