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本帖最后由 Jion 于 2011-03-09 13:46 编辑
回复 1# Jion
POWER7 has these specifications:[6][7]
* 45 nm SOI process, 567 mm2
* 1.2 billion transistors
* 3.0 – 4.25 GHz clock speed
* max 4 chips per quad-chip module
o 4, 6 or 8 cores per chip
+ 4 SMT threads per core (available in AIX 6.1 TL05 (releases in April 2010) and above)
+ 12 execution units per core:
# 2 fixed-point units
# 2 load/store units
# 4 double-precision floating-point units
# 1 vector unit supporting VSX
# 1 decimal floating-point unit
# 1 branch unit
# 1 condition register unit
o 32+32 kB L1 instruction and data cache (per core)[8]
o 256 kB L2 Cache (per core)
o 4 MB L3 cache per core with maximum up to 32MB supported. The cache is implemented in eDRAM, which does not require as many transistors per cell as a standard SRAM[5] so it allows for a larger cache while using the same area as SRAM.
This gives the following theoretical performance figures (based on a 4.04 GHz 8 core implementation):
* max 33.12 GFLOPS per core
* max 264.96 GFLOPS per chip
power74.4GHZ 8core 性能
* max 33.12 GFLOPS per core
* max 264.96 GFLOPS per chip
按照这个算算 ,富士通芯片 |
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