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是这样的,看到Linux编程大全,讲到Makefile,就照着书上写了一个Makefie,如下
EXECUTABLE = test
CC = arm_v5t_le-gcc
CFLAGS = -Wall -g -o2
LDFLAGS =
COMPILE = $(CC) $(CFLAGS)
SRC := $(wildcard *.c)
OBJ := $(patsubst %.c,%.o,$(SRC))
DEP := $(patsubst %.c,%.d,$(SRC))
include $(DEP)
all: $(EXECUTABLE)
$(EXECUTABLE): $(DEP) $(OBJ)
$(CC) $(LDFLAGS) -o $(EXECUTALBE) $(OBJ)
%.o:%.c
@echo "src files: $<"
@echo "object files $@"
$(COMPILE) -c $<
%.d:%.c
$(CC) -M $< > $@
$(CC) -M $< | sed s/[.]o/.d/ >> $@
.PHONY: clean explain depend
clean:
-rm $(OBJ) $(EXECUTABLE) $(DEP) *~
explain:
@echo "begin"
@echo "target is $(EXECUTABLE)"
@echo "Source files: $(SRC)"
@echo "Object files: $(DEP)"
depend: $(DEP)
@echo "Dependencies are now up-to-date"
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我先执行make depend生成依赖文件,这一步正常,然后执行make,但是发现只编译出一个.o文件..
请问高手这是为什么啊 |
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