- 论坛徽章:
- 1
|
读了下手册,下面是intel manual的write through cache type的完整描述:
Write-through (WT) — Writes and reads to and from system memory are cached. Reads come from cache lines on cache hits; read misses cause cache fills. Speculative reads are allowed. All writes are written to a cache line (when possible) and through to system memory. When writing through to memory, invalid cache lines are never filled, and valid cache lines are either filled or invalidated. Write combining is allowed. This type of cache-control is appropriate for frame buffers or when there are devices on the system bus that access system memory, but do not perform snooping of memory accesses. It enforces coherency between caches in the processors and system memory.
我的个人理解是,对UP的机器,要write的address存在两种情况:
1, cache line filled, 这时候,wt的cache line会被再次fill 最新的数据,然后写入RAM.
2, cache line not filled, 这时候,cpu会allocate (if cache not full) and fill cache line, 然后写入RAM.
对MP的机器,假设有A, B两个cpu, A write 某个address,对A来说同UP,对B来说, cache coherency protocal 会使B:
1, B cache line filled, 这时候,wt的cache line会被invalidate, 不会被filled.
2, B cache line not filled, 这时候,nothing to do.
<valid cache lines are either filled or invalidated.> 对A来说是filled (if possible), 对B来说
是invalidated.
以上是个人的理解,仅供参考。 |
|