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原帖由 jyhhappyjyh 于 2009-12-31 11:19 发表 ![]()
MIPS中CPU是否使能MMU是由状态寄存器SR里的TS位决定的吧?而该位是一个只读位,系统reset时初值是“0”,只有当多个TLB出现match时才会置“1”。这就有疑问了,出现多个TLBmatch,怎么就disable MMU了呢?
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这个位是表示相同的虚拟地址映射到了TLB中多个Entry。
status register[TS] bit
Indicates that the TLB has detected a match on multiple
entries. When such a detection occurs, the processor
initiates a machine check exception and sets this bit. It is
implementation dependent whether this condition can be
corrected by software. If the condition can be corrected,
this bit should be cleared by software before resuming
normal operation.
If this bit is not implemented, it must be ignored on write
and read as zero.
Software should not write a 1 to this bit when its value is
a 0, thereby causing a 0-to-1 transition. If such a transition
is caused by software, it is UNPREDICTABLE whether
hardware ignores the write, accepts the write with no side
effects, or accepts the write and initiates a machine check
exception. |
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