ARM9200的spi使用问题

linda_si

大家好：帮忙解决一个困扰我很久的问题啊，急急急！
问题如下：在我的arm9200系统上使用spi扩展了一个MCP2510的SPI转CAN转芯片，还扩展了DM9000A的网卡芯片，我的SPI使用如下：PA0:MISO;PA1:MOSI;PA2:SPCK;PA4:NPCS1,我的DM9000的中断信号线使用：LAN_INIT:PA3/NPCS0/IRQ5,我想SPI口工作在master方式下，采用固定外设方式，DM9000的网卡中断采用IRQ5.我的SPI的驱动程序中，SPI初始化部分如下：
//初始化SPI
void SPI_Init(void)
{  
AT91_SYS->PIOA_PDR =  AT91C_PIO_PA0;  //disable PA0 IO mode
AT91_SYS->PIOA_ASR =  AT91C_PIO_PA0;  //set MISO

AT91_SYS->PIOA_PDR =  AT91C_PIO_PA1;  //disable PA1 IO mode
AT91_SYS->PIOA_ASR =  AT91C_PIO_PA1;  //set MOSI

AT91_SYS->PIOA_PDR =  AT91C_PIO_PA2;  //disable PA2 IO mode
AT91_SYS->PIOA_ASR =  AT91C_PIO_PA2;  //set SPCLK

AT91_SYS->PIOA_PDR =  AT91C_PIO_PA3;  //disable PA3 IO mode
AT91_SYS->PIOA_BSR =  AT91C_PIO_PA3;  //set irq5
  
AT91_SYS->PIOA_PDR =  AT91C_PIO_PA4;  //disable PA4 IO mode
AT91_SYS->PIOA_ASR =  AT91C_PIO_PA4;  //set NPCS1

AT91_SYS->PMC_PCER = 1 << AT91C_ID_SPI;  // Enable Peripheral clock

AT91S_SPI_CFG->SPI_IDR =0x000000ff;  //禁用中断

AT91S_SPI_CFG->SPI_CSR0=0x00000202;
AT91S_SPI_CFG->SPI_CSR1=0x00000202;
AT91S_SPI_CFG->SPI_CSR2=0x00000202;
AT91S_SPI_CFG->SPI_CSR3=0x00000202;
//主机模式，片选直接相连，时钟/32,模式错误检测，固定外设选择，地址为NPCS1
AT91S_SPI_CFG->SPI_MR |= AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_DIV32 | 0xd0000;
AT91S_SPI_CFG->SPI_CR = AT91C_SPI_SPIEN;     // Enable SPI  
}

可是在程序执行的时候，总是说MCP2515无法进入配置模式，读出的状态总是0x00，如果在上面这段spi初始化程序中去掉AT91_SYS->PIOA_BSR =  AT91C_PIO_PA3;  //set irq5 这句，那么MCP2515就工作正常，可是我的DM9000中断需要将其配置为IRQ5这种方式下啊，难道SPI在master方式下，别的NPCS线不能作为其他用法吗？？？请假各位帮忙解决一下，拜托大家了。

[ 本帖最后由 linda_si 于 2009-2-19 15:25 编辑 ]

dreamice

你这个初始化都是宏定义引了的，说实话看不出什么问题。
我建议还是先把自带的spi的datasheet好好看一下，把它的设置和工作模式搞清楚再测试。

wqhl.mark

ATMEL的SPI中设CS没有什么限制，网卡的初始化不要在SPI的初始化程序里设了；同时，检查下网卡初始化部分。

linda_si

谢谢大家对这个问题的回复，我也看到了楼上说的各种意见，但是经过多次仔细琢磨和实验，观察波形，总是不能成功，今天终于看到了at91rm9200的errata，上面有这么一段话：
44. Mode Fault does not allow more than one Master on Chip Select 0
If Mode fault is disabled, Chip Select 0 cannot be driven by a component other than
the SPI otherwise the transfer does not occur.
Problem Fix/Workaround
None.

所以这个问题就是9200本身的bug造成的，而且现在官方也没有给出办法，看来真的只能放弃了，同时又查了官方论坛，如下是Linux-ARM Kernel 的一些帖子：
Can someone confirm that AT91 SPI is working when only using NPCS1 and _not_
NPCS0/NSS?

I use the pin PA3 as IRQ5. Thus I can't use it as NPCS0.

For testing I enabled "Mode Fault Detection" and imideatly the cpu detected
a mode fault (SPI_SR_MODF=1) and disabled the SPI interface
(SPI_SR_SPIENS=0). Obviously he thinks someone is driving a low level to
NPCS0. But as I wrote I havn't configured that pin for NPCS0.

Now I wonder if "Mode Fault Detection" is disabled, will it still be a
problem that NPCS0 is not configured and probably internaly driven to low?

When using a non pdc version of an spi driver I see that SPI_SR_TDRE goes 0
after writing to SPI_TDR. But it never goes 1 again. I don't see any of the
SPI lines change. No Clock. No CS. No Data. ...

Ideas? Anyone?
Author: Steven Scholz
Date: 2006-08-03 20:11 +800
To: Andrew Victor
CC: ARM Linux Mailing List
Subject: Re: Problems with at91spi / at91spidev
=========================================
It does not make sense to enable mode fault detection
if you do not use NPCS0, since mode fault is related to this pin.
Author: Ulf Samuelsson
Date: 2006-08-04 01:16 +800
To: Steven Scholz, ARM Linux Mailing List
Subject: Re: Problems with at91spi / at91spidev
=========================================
Ulf,

>> For testing I enabled "Mode Fault Detection" and imideatly the cpu detected
>> a mode fault (SPI_SR_MODF=1) and disabled the SPI interface
>> (SPI_SR_SPIENS=0). Obviously he thinks someone is driving a low level to
>> NPCS0. But as I wrote I havn't configured that pin for NPCS0.
>>
>> Now I wonder if "Mode Fault Detection" is disabled, will it still be a
>> problem that NPCS0 is not configured and probably internaly driven to low?
>>
>
> It does not make sense to enable mode fault detection
> if you do not use NPCS0, since mode fault is related to this pin.

Can you confirm that SPI (with PDC) works even when Pin NPCS0 is used as IRQ5!?

--
Steven
Author: Steven Scholz
Date: 2006-08-04 15:37 +800
To: Ulf Samuelsson
CC: ARM Linux Mailing List
Subject: Re: Problems with at91spi / at91spidev
==========================================
I hope you have disabled the Dataflash driver in U-Boot and Linux
kernel because it uses NPCS0?
Author: Andreas Schweigstill
Date: 2006-08-04 18:23 +800
To: ARM Linux Mailing List
Subject: Re: Problems with at91spi / at91spidev
======================================
Dear Andreas,

>> Can you confirm that SPI (with PDC) works even when Pin NPCS0 is used
>> as IRQ5!?
>
> I hope you have disabled the Dataflash driver in U-Boot and Linux
> kernel because it uses NPCS0?

Sure. No dataflash support in U-Boot or Kernel.

--
Steven
Author: Steven Scholz
Date: 2006-08-04 18:49 +800
CC: ARM Linux Mailing List
Subject: Re: Problems with at91spi / at91spidev

======================================
到这里这个问题就没有进一步的解决方案了，看来真的如errata 44所说。

谢谢大家，帮我看看这个问题是否真的是这样啊？

linda_si

如下也是：
Author: Steven Scholz
Date: 2006-08-09 16:07 +800
CC: linux-arm-kernel
Subject: Re: using SPI from user space (at91)?

Carsten,

thanks for you reply.

> In function spidev_rd_wr() the following change was necessary for me:
>
> down_read(&mm->mmap_sem);
> -> flush_cache_all(); <-
> err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
> up_read(&mm->mmap_sem);
>
> The line in -> <- is new.
The preferred way would be sending unified diffs like

down_read(&mm->mmap_sem);
+ flush_cache_all();
err= get_user_pages(...
up_read(&mm->mmap_sem);

> adaption logic circuitry was necessary (see for yourself on:
> http://www.siski.de/~carsten/diplomarbeit.html).
Cool.

> The next thing you should check is wether your bootloader correctly
> initializes the PAxx lines needed for SPI to be peripheral function A,
> especially the NPCS0...3 lines if needed.

I want to use PA3 as IRQ5 and not as NPCS0.
Funny enough the SPI stops working when this pin is pulled low externaly.

The AT91 User Manual states:
"A mode fault is detected when the SPI is programmed in Master Mode and a
low level is driven by an external master on the NPCS0/NSS signal.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the
SPI_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the
SPI_CR (Control Register).
By default, Mode Fault Detection is enabled. It is disabled by setting the
MODFDIS bit in the SPI Mode Register."

IIUC I can do whatever I want with the pin PA3 (especially when it's not
configured for SPI at all) iff "Mode Fault Detection" is disabled.
But this is apparently not true.
I am still waiting for ATMEL to confirm on this.
So after leaving PA3 alone SPI works for me.

--
Steven

garyv

你后面禁用中断了，前面set irq5干啥呢？

linda_si

AT91S_SPI_CFG->SPI_IDR =0x000000ff;  //禁用中断
该句禁用的是SPI的中断，是为了后面设置SPI的控制寄存器的，而AT91_SYS->PIOA_BSR =  AT91C_PIO_PA3;  //set irq5只是将PA3定义为B模式，而且PA3也只是将其设置为IRQ5，不使用SPI方式。