I2C Hardware Basic

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I2C Hardware Basic

1.       GENERAL CHARACTERISTICS
I choose five basical feature to give us a general preview of i2c hardware:
1)  Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)
2)  Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard  interface) and can operate as either a transmitter or receiver, depending on the function of the device.
3)  In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
Note: Masters can operate as master-transmitters or as master-receivers
4)  Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus。One clock pulse is generated for each data bit transferred
5)  Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode

2.       DATA TRANSFER
1)       Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.A.1)

Fig1.  Bit transfer on the I2C-bus

2)       START and STOP conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master.
The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.

Fig2.  START and STOP conditions.

3)        Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit.


Fig3.  Data transfer on the I2C-bus.

4)       Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Fig.A.4).Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received, When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.

If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition.


Fig4.  Acknowledge on the I2C-bus.

5)       FORMATS WITH 7-BIT ADDRESSES
Data transfers follow the format shown in Fig.A.5.
After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ).
A data transfer is always terminated by a STOP condition (P) generated by the master.

Fig.A.5  A complete data transfer

Reference:
[1] The IIC-bus specification -v2.1


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