u-boot-1.2.0移植到s3c2410之Nand Flash启动篇

千叶枫

                                                                        U-boot-1.2.0移植到s3c2410之Nand Flash
启动篇
          前一段时间本来打算在ubuntu7.10linux和skyeye 配合下学习arm linux 的开发，搞了一下发现很难搞，本来熟悉arm 和linux已经够头大的了，还需要去熟悉skyeye ，出了很多问题都不知道如何下手解决。感觉skyeye 相关的资料太少也不详细，这只是我个人的感觉。最近下定决心买了个ARMSYS2410开发板子，有了板子发现自己也有学习的动力，做在哪里搞着搞着就发现就下半夜了，而且学习的速度比以前提速了，想学习arm linux 系统的朋友不仿也买个板子。现在的板子也不是很贵，更何况为了学习技术，这点投入也是值得的。

不说废话了，拿到板子后我就开始搞u-boot的移植[color="#000000"]。因为要支持NAND FLASH的读写而且还要增加u-boot nand flash 启动的支持，tftp等功能，我选择的是u-boot-1.2.0，令外一点就是u-booot-1.2.0有现成的交叉编译工具 cross-3.2.tar.bz2 。
        关于如何实现u-boot  nand flash 启动，网上有很多这方面的资料，基本上都是参考vivi源码修改的，大同小异吧。我也是参考网络上的移植方法，再配合vivi 源码（主要是head.s 和nand_read.c)实现u-boot nand flash 启动的。正在进行u-boot移植的朋友，不妨从这两方面入手。
开始移植工作：
1.准备：下载交叉编译工具(cross-3.2.tar.bz2)及 u-boot 源码 u-boot-1.2.0.tar.bz2。cross-3.2.tar.bz2 的安装网上有，不了解的可以网上查下就行了。
2.修改u-boot-1..2.0源 文件
s3c2410开发板与smdk2410基本上一样的，我们可直接在smdk2410基础上修改。具体修改的文件及修改的详细信息如下：
修改配置文件 u-boot-1.2.0/include/config/smdk2410.h
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH
* Marius Groeger
* Gary Jennejohn
* David Mueller
*
* Configuation settings for the SAMSUNG SMDK2410 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T            1    /* This is an ARM920T Core    */
#define    CONFIG_S3C2410          1    /* in a SAMSUNG S3C2410 SoC     */
#define CONFIG_SMDK2410          1    /* on a SAMSUNG SMDK2410 Board  */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ    12000000/* the SMDK2410 has 12MHz input clock */
#define USE_920T_MMU        1
#undef  CONFIG_USE_IRQ            /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN        (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE    128    /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_CS8900    1    /* we have a CS8900 on-board */
#define CS8900_BASE        0x19000300
#define CS8900_BUS16        1 /* the Linux driver does accesses as shorts */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1          1    /* we use SERIAL 1 on SMDK2410 */
/************************************************************
* RTC
************************************************************/
#define    CONFIG_RTC_S3C24X0    1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE        115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_COMMANDS \
            (CONFIG_CMD_DFL     | \
            CFG_CMD_CACHE     | \
            CFG_CMD_NAND     | \   /*Nand Flash 支持*/
            /*CFG_CMD_EEPROM |*/ \
            /*CFG_CMD_I2C     |*/ \
            /*CFG_CMD_USB     |*/ \
            CFG_CMD_REGINFO  | \
            CFG_CMD_DATE     | \
               /*FG_CMD_KGDB     |*/\
            CFG_CMD_NET     | \ /*网络支持*/            CFG_CMD_PING    |\ /*ping 功能*/
            CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include
#define CONFIG_BOOTDELAY        5
#define CONFIG_BOOTARGS    " noinitrd root=/dev/mtdblock/2\  
init=/linuxrc console=ttySAC0,115200" /*传递给linux 的启动参数*/
#define CONFIG_ETHADDR            08:00:3e:26:0a:5b#define CONFIG_NETMASK             255.255.255.0     /*这里是配置s3c2410的网络*/#define CONFIG_IPADDR               192.168.1.110        /*为后面的tftp 功能做准备*/#define CONFIG_SERVERIP           192.168.1.101        
/*#define CONFIG_BOOTFILE        "elinos-lart" */
#define CONFIG_BOOTCOMMAND    "nand read 30008000 140000 200000\; bootm 30008000"  /*u-boot 启动后执行的命令 这里的命令是从Nand Flash 0x140000的位置加载操作系统到 DRAM的 0x30008000 的位置 大小为 2M（文件大小取决于你的系统大小，这里的地址及文件大小要求为512的整数倍）*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE    115200        /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX    1        /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define    CFG_LONGHELP                /* undef to save memory        */
#define    CFG_PROMPT        "SMDK2410 # "    /* Monitor Command Prompt    */
#define    CFG_CBSIZE        256        /* Console I/O Buffer Size    */
#define    CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define    CFG_MAXARGS        16        /* max number of command args    */
#define CFG_BARGSIZE    CFG_CBSIZE    /* Boot Argument Buffer Size    */
#define CFG_MEMTEST_START    0x30000000    /* memtest works on    */
#define CFG_MEMTEST_END        0x33F00000    /* 63 MB in DRAM    */
#undef  CFG_CLKS_IN_HZ        /* everything, incl board info, in Hz */
#define    CFG_LOAD_ADDR        0x30008000     /* default load address    */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define    CFG_HZ                1562500
/* valid baudrates */
#define CFG_BAUDRATE_TABLE    { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE        (128*1024)    /* regular stack */
#ifdef     CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)    /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)    /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS    1       /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1        0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE    0x04000000 /* 64 MB */
#define PHYS_FLASH_1        0x00000000 /* Flash Bank #1 */
#define CFG_FLASH_BASE        PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
//#define CONFIG_AMD_LV400    1    /* uncomment this if you have a LV400 flash */#define CONFIG_AMD_LV800    1        /* uncomment this if you have a LV800 flash */
//#define CFG_NO_FLASH            1
#define CFG_MAX_FLASH_BANKS    1    /* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE        0x00100000 /* 1MB */
#define CFG_MAX_FLASH_SECT    (19)    /* max number of sectors on one chip */
#define CFG_ENV_ADDR        (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE        0x00020000 /* 128KB */
#define CFG_MAX_FLASH_SECT    (11)    /* max number of sectors on one chip */
#define CFG_ENV_ADDR        (CFG_FLASH_BASE + 0x070000) /* addr of environment */
#endif
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT    (5*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT    (5*CFG_HZ) /* Timeout for Flash Write */
/*环境变量存放位置 Nand Flash Offset=0x00020000  预留空间大小为64K*/
#define    CFG_ENV_IS_IN_NAND    1  #define CFG_ENV_OFFSET          0x00020000   /*128k*/#define CFG_ENV_SIZE      0x10000          /* 64kTotal Size of Environment Sector */
/*Nand Flash 相关配置项*/#if (CONFIG_COMMANDS & CFG_CMD_NAND)#define CFG_NAND_LEGACY       1     /* 启用 driver/nand_legacy/nand_legacy.c *///#define CONFIG_MTD_NAND_VERIFY_WRITE    1 #define CFG_MAX_NAND_DEVICE   1     /* Max number of NAND devices        */#define SECTORSIZE 512#define NAND_SECTOR_SIZE SECTORSIZE#define NAND_BLOCK_MASK 511#define ADDR_COLUMN     1#define ADDR_PAGE         2#define ADDR_COLUMN_PAGE     3

#define NAND_ChipID_UNKNOWN   0x00#define NAND_MAX_FLOORS 1#define NAND_MAX_CHIPS 1

/*Nand Flash 底层驱动，Nand Flash Controller 寄存器读写*/
#define NAND_WAIT_READY(nand)           do{ while(!(rNFSTAT&(1#define NAND_DISABLE_CE(nand)           do{ rNFCONF |= (1#define NAND_ENABLE_CE(nand)            do{ rNFCONF &= ~(1#define WRITE_NAND_COMMAND(d, adr)      do{ rNFCMD  = d; }while(0);#define WRITE_NAND_ADDRESS(d, adr)      do{ rNFADDR = d; }while(0);#define WRITE_NAND(d, adr)                     do{ rNFDATA = d; }while(0);#define READ_NAND(adr)                         (rNFDATA)/* the following functions are NOP's because S3C24X0 handles this in hardware */#define NAND_CTL_CLRALE(nandptr)#define NAND_CTL_SETALE(nandptr)#define NAND_CTL_CLRCLE(nandptr)#define NAND_CTL_SETCLE(nandptr)
/*LED灯 为了调试用*/#define CONFIG_DEBUG_LED             1         #define CONFIG_S3C2410_NAND_BOOT     1 /*boot from nand flash*/#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
//#define CONFIG_SHOW_INFOMATION 1     /*printf some infomation*/
/*显示调试信息*/#ifdef  CONFIG_SHOW_INFOMATION//#define DEBUG               1#define NAND_DEBUG        1//#define CONFIG_DISPLAY_CPUINFO 1 /*CPU*///#define CONFIG_DISPLAY_BOARDINFO 1 /*BOARD*/#endif
#define CONFIG_IDENT_STRIN  " 2008/6/4 AVICI SADRI Liuwei"
#endif    /* __CONFIG_H */
修改 u-boot-1.2.0/cpu/arm920t/start.S
/*
* armboot - Startup Code for ARM920 CPU-core
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include
#include
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start:    b       reset
    ldr    pc, _undefined_instruction
    ldr    pc, _software_interrupt
    ldr    pc, _prefetch_abort
    ldr    pc, _data_abort
    ldr    pc, _not_used
    ldr    pc, _irq
    ldr    pc, _fiq
_undefined_instruction:    .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:        .word not_used
_irq:            .word irq
_fiq:            .word fiq
    .balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
_TEXT_BASE:
    .word    TEXT_BASE
.globl _armboot_start
_armboot_start:
    .word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
    .word __bss_start
.globl _bss_end
_bss_end:
    .word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
    .word    0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
    .word 0x0badc0de
#endif
/*
* the actual reset code
*/
reset:
    /*
     * set the cpu to SVC32 mode
     */
    mrs    r0,cpsr
    bic    r0,r0,#0x1f
    orr    r0,r0,#0xd3
    msr    cpsr,r0
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON        0x15300000
# define INTMSK        0x14400008    /* Interupt-Controller base addresses */
# define CLKDIVN    0x14800014    /* clock divisor register */
#elif defined(CONFIG_S3C2410)
# define pWTCON        0x53000000
# define INTMSK        0x4A000008    /* Interupt-Controller base addresses */
# define INTSUBMSK    0x4A00001C
# define CLKDIVN        0x4C000014      /* clock divisor register */
#endif
#ifdef CONFIG_DEBUG_LED
/*LED 控制寄存器*/#define GPFCON       0x56000050#define GPFUP         0x56000058#define GPFDATA    0x56000054#endif
#define STACK_BASE    0x33f00000#define STACK_SIZE    0x8000
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
        /*watch dog*/
    ldr     r0, =pWTCON
    mov     r1, #0x0
    str     r1, [r0]
    /*
     * mask all IRQs by setting all bits in the INTMR - default
     */
    mov    r1, #0xffffffff
    ldr    r0, =INTMSK
    str    r1, [r0]
# if defined(CONFIG_S3C2410)
    ldr    r1, =0x3ff
    ldr    r0, =INTSUBMSK
    str    r1, [r0]
# endif
    /*FCLK:HCLK:PCLK = 1:2:4 */
    ldr    r0, =CLKDIVN
    mov    r1, #3
    str    r1, [r0]
#endif    /* CONFIG_S3C2400 || CONFIG_S3C2410 */
#ifdef CONFIG_DEBUG_LED
/*初始化 led */        bl      init_led#endif   
/*
         * we do sys-critical inits only at reboot,
         * not when booting from ram!
         */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT   
relocate:
    /* relocate U-Boot to RAM        */
    adr    r0, _start        /* r0 #ifdef CONFIG_S3C2410_NAND_BOOT    /* CONFIG_S3C2410_NAND_BOOT */
        /*boot from Nand Flash */        bl    copy_myself        b     stack_setup#else     ldr    r2, _armboot_start    ldr    r3, _bss_start    sub    r2, r3, r2        /* r2     add    r2, r0, r2        /* r2 copy_loop:    ldmia    r0!, {r3-r10}        /* copy from source address [r0]    */    stmia    r1!, {r3-r10}        /* copy to   target address [r1]    */    cmp    r0, r2            /* until source end addreee [r2]    */    ble    copy_loop#endif
#endif    /* CONFIG_SKIP_RELOCATE_UBOOT */
    /* Set up the stack                            */
stack_setup:
    ldr    r0, _TEXT_BASE        /* upper 128 KiB: relocated uboot   */
    sub    r0, r0, #CFG_MALLOC_LEN    /* malloc area                      */
    sub    r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
#ifdef CONFIG_USE_IRQ
    sub    r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
    sub    sp, r0, #12        /* leave 3 words for abort-stack    */
clear_bss:
    ldr    r0, _bss_start        /* find start of bss segment        */
    ldr    r1, _bss_end        /* stop here                        */
    mov     r2, #0x00000000        /* clear                            */
clbss_l:str    r2, [r0]        /* clear loop...                    */
    add    r0, r0, #4
    cmp    r0, r1
    ble    clbss_l
/*#ifdef CONFIG_DEBUG_LED
dead_loop:
        ldr r3,=GPFDATA
        mov r1,#0x1f
        str r1,[r3]
        b dead_loop
#endif  */
/*just to asure the program can run to here*/
    ldr    pc, _start_armboot
_start_armboot:    .word start_armboot
#ifdef CONFIG_DEBUG_LED/*LED control register */init_led:        ldr  r0, =GPFCON        ldr  r1, =0x55aa        str r1,[r0]             ldr r0,=GPFUP        mov r1,#0xff        str r1,[r0]        ldr r0,=GPFDATA        mov r1,#ff        str r1,[r0]        mov pc,lr#endif
#ifdef CONFIG_S3C2410_NAND_BOOT#define NAND_CTL_BASE 0x4e000000#define oNFCONF 0x00      #define oNFCMD  0x04#define oNFSTAT 0x10copy_myself:    mov r10, lr    /*rest*/    ldr    r1, =NAND_CTL_BASE    ldr    r2, =0xf830        @ initial value    str    r2, [r1, #oNFCONF]    ldr    r2, [r1, #oNFCONF]    bic    r2, r2, #0x800        @ enable chip    str    r2, [r1, #oNFCONF]    mov    r2, #0xff        /*RESET command*/    strb   r2, [r1, #oNFCMD]    mov    r3, #0            /* wait*/1:  add    r3, r3, #0x1    cmp    r3, #0xa    blt    1b2:  ldr    r2, [r1, #oNFSTAT]    /*wait ready*/    tst    r2, #0x1    beq    2b    ldr    r2, [r1, #oNFCONF]    orr    r2, r2, #0x800        /*disable chip*/    str    r2, [r1, #oNFCONF] /*end of nand rest*/            ldr r0, =TEXT_BASE      mov r1, #0x0                            mov r2, #0x20000     ldr sp, DW_STACK_START      mov fp, #0                    bl nand_read_whole              tst r0, #0x0                            beq ok_nand_readbad_nand_read:loop2:#ifdef  CONFIG_DEBUG_LED        ldr r3,=GPFDATA        mov r1,#0xbf /*LED3*/        str r1,[r3]#endif        b     loop2  /*error !!infinite loop please reset */ok_nand_read:          /*verfy */        mov     r0, #0        ldr     r1, =TEXT_BASE        mov     r2, #0x400     /*4 bytes * 1024 = 4K-bytes*/next:        ldr   r3, [r0], #4        ldr   r4, [r1], #4        teq   r3, r4        bne   notmatch        subs  r2, r2, #4        beq    done_nand_read            bne   nextnotmatch:loop3:  #ifdef CONFIG_DEBUG_LED        ldr r3,=GPFDATA        mov r1,#0x9f        str r1,[r3] /*LED2 LED3*/#endif        b      loop3         /*infinite loop*/done_nand_read:        mov    pc, r10.align 2DW_STACK_START:         .word  STACK_BASE+STACK_SIZE-4#endif
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
    /*
     * flush v4 I/D caches
     */
    mov    r0, #0
    mcr    p15, 0, r0, c7, c7, 0    /* flush v3/v4 cache */
    mcr    p15, 0, r0, c8, c7, 0    /* flush v4 TLB */
    /*
     * disable MMU stuff and caches
     */
    mrc    p15, 0, r0, c1, c0, 0
    bic    r0, r0, #0x00002300    @ clear bits 13, 9:8 (--V- --RS)
    bic    r0, r0, #0x00000087    @ clear bits 7, 2:0 (B--- -CAM)
    orr    r0, r0, #0x00000002    @ set bit 2 (A) Align
    orr    r0, r0, #0x00001000    @ set bit 12 (I) I-Cache
    mcr    p15, 0, r0, c1, c0, 0
    /*
     * before relocating, we have to setup RAM timing
     * because memory timing is board-dependend, you will
     * find a lowlevel_init.S in your board directory.
     */
    mov    ip, lr
    bl    lowlevel_init
    mov    lr, ip
    mov    pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE    72
#define S_OLD_R0    68
#define S_PSR        64
#define S_PC        60
#define S_LR        56
#define S_SP        52
#define S_IP        48
#define S_FP        44
#define S_R10        40
#define S_R9        36
#define S_R8        32
#define S_R7        28
#define S_R6        24
#define S_R5        20
#define S_R4        16
#define S_R3        12
#define S_R2        8
#define S_R1        4
#define S_R0        0
#define MODE_SVC 0x13
#define I_BIT     0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
    .macro    bad_save_user_regs
    sub    sp, sp, #S_FRAME_SIZE
    stmia    sp, {r0 - r12}            @ Calling r0-r12
    ldr    r2, _armboot_start
    sub    r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
    sub    r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
    ldmia    r2, {r2 - r3}            @ get pc, cpsr
    add    r0, sp, #S_FRAME_SIZE        @ restore sp_SVC
    add    r5, sp, #S_SP
    mov    r1, lr
    stmia    r5, {r0 - r3}            @ save sp_SVC, lr_SVC, pc, cpsr
    mov    r0, sp
    .endm
    .macro    irq_save_user_regs
    sub    sp, sp, #S_FRAME_SIZE
    stmia    sp, {r0 - r12}            @ Calling r0-r12
    add     r8, sp, #S_PC
    stmdb   r8, {sp, lr}^                   @ Calling SP, LR
    str     lr, [r8, #0]                    @ Save calling PC
    mrs     r6, spsr
    str     r6, [r8, #4]                    @ Save CPSR
    str     r0, [r8, #8]                    @ Save OLD_R0
    mov    r0, sp
    .endm
    .macro    irq_restore_user_regs
    ldmia    sp, {r0 - lr}^            @ Calling r0 - lr
    mov    r0, r0
    ldr    lr, [sp, #S_PC]            @ Get PC
    add    sp, sp, #S_FRAME_SIZE
    subs    pc, lr, #4            @ return & move spsr_svc into cpsr
    .endm
    .macro get_bad_stack
    ldr    r13, _armboot_start        @ setup our mode stack
    sub    r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
    sub    r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
    str    lr, [r13]            @ save caller lr / spsr
    mrs    lr, spsr
    str     lr, [r13, #4]
    mov    r13, #MODE_SVC            @ prepare SVC-Mode
    @ msr    spsr_c, r13
    msr    spsr, r13
    mov    lr, pc
    movs    pc, lr
    .endm
    .macro get_irq_stack            @ setup IRQ stack
    ldr    sp, IRQ_STACK_START
    .endm
    .macro get_fiq_stack            @ setup FIQ stack
    ldr    sp, FIQ_STACK_START
    .endm
/*
* exception handlers
*/
    .align  5
undefined_instruction:
    get_bad_stack
    bad_save_user_regs
    bl     do_undefined_instruction
    .align    5
software_interrupt:
    get_bad_stack
    bad_save_user_regs
    bl     do_software_interrupt
    .align    5
prefetch_abort:
    get_bad_stack
    bad_save_user_regs
    bl     do_prefetch_abort
    .align    5
data_abort:
    get_bad_stack
    bad_save_user_regs
    bl     do_data_abort
    .align    5
not_used:
    get_bad_stack
    bad_save_user_regs
    bl     do_not_used
#ifdef CONFIG_USE_IRQ
    .align    5
irq:
    get_irq_stack
    irq_save_user_regs
    bl     do_irq
    irq_restore_user_regs
    .align    5
fiq:
    get_fiq_stack
    /* someone ought to write a more effiction fiq_save_user_regs */
    irq_save_user_regs
    bl     do_fiq
    irq_restore_user_regs
#else
    .align    5
irq:
    get_bad_stack
    bad_save_user_regs
    bl     do_irq
    .align    5
fiq:
    get_bad_stack
    bad_save_user_regs
    bl     do_fiq
#endif
增加nand_read.cu-boot-1.2.0/board/smdk2410/nand_read.c
#include #define __REGb(x)    (*(volatile unsigned char *)(x))#define __REGi(x)    (*(volatile unsigned int *)(x))#define NF_BASE        0x4e000000#define NFCONF        __REGi(NF_BASE + 0x0)#define NFCMD         __REGb(NF_BASE + 0x4)#define NFADDR        __REGb(NF_BASE + 0x8)#define NFDATA        __REGb(NF_BASE + 0xc)#define NFSTAT        __REGb(NF_BASE + 0x10)#define BUSY 1inline void wait_idle(void) {    int i;    while(!(NFSTAT & BUSY))      for(i=0; i}/*low level nand read function */int nand_read_whole(unsigned char *buf, unsigned long start_addr, int size){    int i, k;    if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK))     {        return -1;    /* invalid alignment */    }    /* chip Enable */    NFCONF &= ~0x800;    for(i=0; i    for(i=start_addr; i    {      /* READ0 */      NFCMD = 0;      /* Write Address */      NFADDR = i & 0xff;      NFADDR = (i >> 9) & 0xff;      NFADDR = (i >> 17) & 0xff;      NFADDR = (i >> 25) & 0xff;      wait_idle();      for(k=0; k      {        *buf = (NFDATA & 0xff);        buf++;      }   }    /* chip Disable */   NFCONF |= 0x800;    /* chip disable */   return 0;}

修改u-boot-1.2.0/board/smdk2410/Makefile
将原 COBJS    := smdk2410.o flash.o
改为 COBJS    := nand_read.o smdk2410.o flash.o   
修改 u-boot-1.2.0/board/smdk2410/lowlel_init.S
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
*                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
* David Mueller, ELSOFT AG,
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include
#include
/* some parameters for the board */
/*
*
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
*
* Copyright (C) 2002 Samsung Electronics SW.LEE  
*
*/
#define BWSCON    0x48000000
/* BWSCON */
#define DW8             (0x0)
#define DW16             (0x1)
#define DW32             (0x2)
#define WAIT             (0x1/*这里要配置好否则 cs8900a网卡不能正常运行*/
#define B3_Tacs             0x0    /*  0clk */#define B3_Tcos             0x3    /*  4clk */#define B3_Tacc             0x7    /* 14clk */
#define B3_Tcoh             0x1    /*  1clk */#define B3_Tah              0x3     /*  4clk */#define B3_Tacp             0x3    /*  6clk */#define B3_PMC              0x0     /* normal */
#define B4_Tacs             0x0    /*  0clk */
#define B4_Tcos             0x0    /*  0clk */
#define B4_Tacc             0x7    /* 14clk */
#define B4_Tcoh             0x0    /*  0clk */
#define B4_Tah             0x0    /*  0clk */
#define B4_Tacp             0x0
#define B4_PMC             0x0    /* normal */
#define B5_Tacs             0x0    /*  0clk */
#define B5_Tcos             0x0    /*  0clk */
#define B5_Tacc             0x7    /* 14clk */
#define B5_Tcoh             0x0    /*  0clk */
#define B5_Tah             0x0    /*  0clk */
#define B5_Tacp             0x0
#define B5_PMC             0x0    /* normal */
#define B6_MT             0x3    /* SDRAM */
#define B6_Trcd              0x1
#define B6_SCAN             0x1    /* 9bit */
#define B7_MT             0x3    /* SDRAM */
#define B7_Trcd             0x1    /* 3clk */
#define B7_SCAN             0x1    /* 9bit */
/* REFRESH parameter */
#define REFEN             0x1    /* Refresh enable */
#define TREFMD             0x0    /* CBR(CAS before RAS)/Auto refresh */
#define Trp             0x0    /* 2clk */
#define Trc             0x3    /* 7clk */
#define Tchr             0x2    /* 3clk */
#define REFCNT             1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE:
    .word    TEXT_BASE
.globl lowlevel_init
lowlevel_init:
    /* memory control configuration */
    /* make r0 relative the current location so that it */
    /* reads SMRDATA out of FLASH rather than memory ! */
    ldr     r0, =SMRDATA
    ldr    r1, _TEXT_BASE
    sub    r0, r0, r1
    ldr    r1, =BWSCON    /* Bus Width Status Controller */
    add     r2, r0, #13*4
0:
    ldr     r3, [r0], #4
    str     r3, [r1], #4
    cmp     r2, r0
    bne     0b
    /* everything is fine now */
    mov    pc, lr
    .ltorg
/* the literal pools origin */
SMRDATA:
    .word (0+(B1_BWSCON .word 0xb2
    .word 0x30
    .word 0x30
    最后编译 ，将u-boot.bin 文件烧到Nand Flash （从0开始的位置进行烧写）。打开minicom ,启动板子，如果幸运的话就可以了看到，u-boot 的启动信息了，哈哈。
下一篇介绍，如何利用nand_leagcy实现Nand Flash 的读写及实现tftp 下载。
               
               
               
               
               
               
               
               
               
               
               

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