volatile 和 内存屏障

sonicling

volatile号称保证单CPU单个对象的访问顺序，但是Cache、乱序都有可能使它成为一句空话，结果volatile只剩下一个保证了，那就是保证读写不会被优化掉，这只是它的号称的一个附加效果。

内存屏障跟切换没关系，单x86下用不用内存屏障都没什么区别。内存屏障针对多CPU下，一个CPU等待另外一个CPU的结果。

瀚海书香

回复 11# sonicling

单x86下用不用内存屏障都没什么区别。内存屏障针对多CPU下，一个CPU等待另外一个CPU的结果。

   
个人认为这句话应该是不正确的。在单CPU的情况下，也是需要内存屏障的。比如CPU和外设交互的情形。

tempname2

线程共用寄存器？
x86上cache需要软件担心一致性问题？
内存屏障？write buffer？

tempname2

回复 11# sonicling


   

Some devices present their control interfaces as collections of memory
locations, but the order in which the control registers are accessed is very
important.  For instance, imagine an ethernet card with a set of internal
registers that are accessed through an address port register (A) and a data
port register (D).  To read internal register 5, the following code might then
be used:

        *A = 5;
        x = *D;

but this might show up as either of the following two sequences:

        STORE *A = 5, x = LOAD *D
        x = LOAD *D, STORE *A = 5

the second of which will almost certainly result in a malfunction, since it set
the address _after_ attempting to read the register.

sonicling

回复 12# 瀚海书香
回复 14# tempname2


    的确。涉及到乱序，还是要靠内存屏障。