新手求助:T2000宕机

ztejob

以下是做最大化自检的输出，怀疑是主板坏了
sc> console
Enter #. to return to ALOM.
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SC Alert: Host System has Reset
2011-12-14 03:14:18.768 0:0:0>
2011-12-14 03:14:18.811 0:0:0>Sun Fire[TM] T2000 POST 4.28.6 2008/05/23 12:30
       /export/delivery/delivery/4.28/4.28.6/post4.28.x/Niagara/ontario/integrated  (root)  
2011-12-14 03:14:19.024 0:0:0>Copyright 2008 Sun Microsystems, Inc. All rights reserved
2011-12-14 03:14:19.137 0:0:0>VBSC cmp0 arg is: ffffffff.00000311
2011-12-14 03:14:19.225 0:0:0>POST enabling threads: 00000000.ffffffff
2011-12-14 03:14:19.322 0:0:0>VBSC cntl arg is: ffffffff.00000311
2011-12-14 03:14:19.410 0:0:0>VBSC selecting POST MAX Testing.
2011-12-14 03:14:19.497 0:0:0>VBSC setting verbosity level 3
2011-12-14 03:14:19.585 0:0:0>  Niagara, Version 2.0
2011-12-14 03:14:19.661 0:0:0>  Serial Number = fffffa29.ac6dc5c6
2011-12-14 03:14:19.752 0:0:0>Start Selftest.....
2011-12-14 03:14:19.836 0:0:0>Begin: Init CPU
2011-12-14 03:14:19.916 0:0:0>End  : Init CPU
2011-12-14 03:14:19.984 0:0:0>Master CPU Tests Basic.....
2011-12-14 03:14:20.086 0:0:0>CPU =: 0
2011-12-14 03:14:20.177 0:0:0>Begin: DMMU Registers Access
2011-12-14 03:14:20.424 0:0:0>End  : DMMU Registers Access
2011-12-14 03:14:20.512 0:0:0>Begin: IMMU Registers Access
2011-12-14 03:14:20.725 0:0:0>End  : IMMU Registers Access
2011-12-14 03:14:20.814 0:0:0>Begin: Common MMU regs
2011-12-14 03:14:21.054 0:0:0>End  : Common MMU regs
2011-12-14 03:14:21.138 0:0:0>Begin: Init mmu regs
2011-12-14 03:14:21.234 0:0:0>End  : Init mmu regs
2011-12-14 03:14:21.322 0:0:0>Begin: D-Cache RAM
2011-12-14 03:14:22.647 0:0:0>End  : D-Cache RAM
2011-12-14 03:14:22.727 0:0:0>Init MMU.....
2011-12-14 03:14:25.260 0:0:0>Begin: Setup DMMU Miss Handler
2011-12-14 03:14:25.362 0:0:0>End  : Setup DMMU Miss Handler
2011-12-14 03:14:25.459 0:0:0>Begin: Init JBUS Config Regs
2011-12-14 03:14:25.558 0:0:0>End  : Init JBUS Config Regs
2011-12-14 03:14:25.682 0:0:0>Begin: IO-Bridge unit 1 init test            
2011-12-14 03:14:27.784 0:0:0>End  : IO-Bridge unit 1 init test            
2011-12-14 03:14:28.903 0:0:0>Sys 200 MHz, CPU 1200 MHz, Mem 200 MHz
2011-12-14 03:14:29.019 0:0:0>Begin: Integrated POST Testing
2011-12-14 03:14:29.124 0:0:0>End  : Integrated POST Testing
2011-12-14 03:14:29.214 0:0:0>L2 Tests.....
2011-12-14 03:14:29.290 0:0:0>Begin: Setup L2 Cache
2011-12-14 03:14:29.374 0:0:0>L2 Cache Control = 00000000.00300000
2011-12-14 03:14:29.481 0:0:0>End  : Setup L2 Cache
2011-12-14 03:14:29.566 0:0:0>Begin: L2 Cache UA Array Test
2011-12-14 03:14:30.242 0:0:0>End  : L2 Cache UA Array Test
2011-12-14 03:14:30.331 0:0:0>Begin: L2 Cache VD Array Test
2011-12-14 03:14:31.007 0:0:0>End  : L2 Cache VD Array Test
2011-12-14 03:14:31.097 0:0:0>Begin: L2 Cache Tags Test
2011-12-14 03:14:38.203 0:0:0>End  : L2 Cache Tags Test
2011-12-14 03:14:38.288 0:0:0>Begin: Scrub and Setup L2 Cache
2011-12-14 03:14:38.380 0:0:0>L2 Directory clear
2011-12-14 03:14:38.452 0:0:0>L2 Scrub VD & UA
2011-12-14 03:14:38.654 0:0:0>L2 Scrub Tags
2011-12-14 03:14:40.056 0:0:0>End  : Scrub and Setup L2 Cache
2011-12-14 03:14:40.146 0:0:0>Test Memory.....
2011-12-14 03:14:40.225 0:0:0>Begin: Probe and Setup Memory
2011-12-14 03:14:40.313 0:0:0>INFO:       8192MB at Memory Channel [0 1 2 3 ] Rank 0 Stack 0
2011-12-14 03:14:40.467 0:0:0>INFO:          0MB at Memory Channel [0 1 2 3 ] Rank 0 Stack 1
2011-12-14 03:14:40.622 0:0:0>INFO:       8192MB at Memory Channel [0 1 2 3 ] Rank 1 Stack 0
2011-12-14 03:14:40.776 0:0:0>INFO:          0MB at Memory Channel [0 1 2 3 ] Rank 1 Stack 1
2011-12-14 03:14:40.931 0:0:0>
2011-12-14 03:14:40.989 0:0:0>End  : Probe and Setup Memory
2011-12-14 03:14:41.080 0:0:0>Begin: Data Bitwalk
2011-12-14 03:14:41.155 0:0:0>L2 Scrub Data
2011-12-14 03:15:08.525 0:0:0>L2 Enable
2011-12-14 03:15:08.585 0:0:0>  Testing Memory Channel 0 Rank 0 Stack 0
2011-12-14 03:15:10.652 0:0:0>  Testing Memory Channel 1 Rank 0 Stack 0
2011-12-14 03:15:12.716 0:0:0>  Testing Memory Channel 2 Rank 0 Stack 0
2011-12-14 03:15:14.782 0:0:0>  Testing Memory Channel 3 Rank 0 Stack 0
2011-12-14 03:15:16.850 0:0:0>  Testing Memory Channel 0 Rank 1 Stack 0
2011-12-14 03:15:18.914 0:0:0>  Testing Memory Channel 1 Rank 1 Stack 0
2011-12-14 03:15:20.979 0:0:0>  Testing Memory Channel 2 Rank 1 Stack 0
2011-12-14 03:15:23.043 0:0:0>  Testing Memory Channel 3 Rank 1 Stack 0
2011-12-14 03:15:25.107 0:0:0>L2 Directory clear
2011-12-14 03:15:25.179 0:0:0>L2 Scrub VD & UA
2011-12-14 03:15:25.381 0:0:0>L2 Scrub Tags
2011-12-14 03:15:26.766 0:0:0>L2 Disable
2011-12-14 03:15:26.832 0:0:0>End  : Data Bitwalk
2011-12-14 03:15:26.915 0:0:0>Begin: Address Bitwalk
2011-12-14 03:15:26.993 0:0:0>  Testing Memory Channel 0 Rank 0 Stack 0
2011-12-14 03:15:27.549 0:0:0>  Testing Memory Channel 1 Rank 0 Stack 0
2011-12-14 03:15:28.106 0:0:0>  Testing Memory Channel 2 Rank 0 Stack 0
2011-12-14 03:15:28.663 0:0:0>  Testing Memory Channel 3 Rank 0 Stack 0
2011-12-14 03:15:29.222 0:0:0>  Testing Memory Channel 0 Rank 1 Stack 0
2011-12-14 03:15:29.768 0:0:0>  Testing Memory Channel 1 Rank 1 Stack 0
2011-12-14 03:15:30.317 0:0:0>  Testing Memory Channel 2 Rank 1 Stack 0
2011-12-14 03:15:30.864 0:0:0>  Testing Memory Channel 3 Rank 1 Stack 0
2011-12-14 03:15:31.420 0:0:0>End  : Address Bitwalk
2011-12-14 03:15:31.507 0:0:0>Setup POST Mailbox .....
2011-12-14 03:15:31.601 0:0:0>Begin: Test Mailbox region
2011-12-14 03:15:31.680 0:0:0>..
2011-12-14 03:15:47.456 0:0:0>End  : Test Mailbox region
2011-12-14 03:15:47.543 0:0:0>Begin: Set Mailbox
2011-12-14 03:15:49.127 0:0:0>Begin: Setup Final DMMU Entries
2011-12-14 03:15:49.236 0:0:0>End  : Setup Final DMMU Entries
2011-12-14 03:15:49.353 0:0:0>Begin: Post Image Region Scrub
2011-12-14 03:15:49.825 0:0:0>End  : Post Image Region Scrub
2011-12-14 03:15:49.917 0:0:0>Begin: Run POST from Memory
2011-12-14 03:15:59.167 0:0:0>Verifying checksum on copied image.
2011-12-14 03:15:59.254 0:0:0>The Memory's CHECKSUM value is d445.
2011-12-14 03:15:59.342 0:0:0>The Memory's Content Size value is 8b412.
2011-12-14 03:16:07.140 0:0:0>Success...  Checksum on Memory Validated.
2011-12-14 03:16:07.244 0:0:0>End  : Run POST from Memory
2011-12-14 03:16:07.325 0:0:0>Begin: L2 Cache Ram Test
2011-12-14 03:16:09.303 0:0:0>
2011-12-14 03:16:09.310 0:0:0>ERROR: TEST = L2 Cache Ram Test
2011-12-14 03:16:09.329 0:0:0>H/W under test =  L2-Cache
2011-12-14 03:16:09.348 0:0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2011-12-14 03:16:09.381 0:0:0>MSG =     Pre-Read Data error
                Adddress 000000a0.006c0040
                EXP = 00000000.00000000
                OBS = 00000000.00000010
2011-12-14 03:16:09.422 0:0:0>END_ERROR

2011-12-14 03:16:10.718 0:0:0>
2011-12-14 03:16:10.726 0:0:0>ERROR: TEST = L2 Cache Ram Test
2011-12-14 03:16:10.745 0:0:0>H/W under test =  L2-Cache
2011-12-14 03:16:10.764 0:0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2011-12-14 03:16:10.794 0:0:0>MSG =
         *** Test Failed!! ***

2011-12-14 03:16:10.812 0:0:0>END_ERROR

2011-12-14 03:16:10.821 0:0:0>End  : L2 Cache Ram Test
2011-12-14 03:16:10.842 0:0:0>ERROR: POST terminated prematurely. Not all system components tested
2011-12-14 03:16:10.872 0:0:0>POST:     Return to VBSC
2011-12-14 03:16:10.889 0:0:0>ERROR:
2011-12-14 03:16:10.897 0:0:0>  POST toplevel status has the following failures:
2011-12-14 03:16:10.919 0:0:0>          MB/CMP0 (L2 Cache)
2011-12-14 03:16:10.940 0:0:0>END_ERROR

2011-12-14 03:16:10.947 0:0:0>Master set ACK for vbsc runpost command and spin...
\
SC Alert: Host system has shut down.
/
SC Alert: Host System has Reset
DEC 14 03:00:37 ERROR: HV Abort: <Unknown?> (21718c) - PowerDown
-
SC Alert: Host system has shut down.

ztejob

T2000可以单独更换CPU吗还是主机跟CPU是一体的？

ztejob

T2000可以单独更换CPU吗还是主板跟CPU是一体的？

killer911

换主板

8894106

{:3_185:}换主板吧，貌似T2000没有独立的CPU

财版

CPUcache坏了

鑫杰

CPU其实是可以单独换的

东方蜘蛛

CPU其实是可以单独换的
鑫杰 发表于 2011-12-15 11:14

    CACHE能单独换么

ztejob

今天更换了主板，一切OK