开始一直以为是DM9000的BASE没有选对,但是对照了光盘上带的VIVI查看,发现是0X19000300.(DM9000AEP的CS接nGCS3,CMD接LADDR2)
今天终于运气来了,实然想知道DM9000是如何对寄存器进行读写的。百度了一篇很不错的文章,专门讲了一下DM9000的寄存器读写时序问题。文中谈到了移植DM9000驱动时要修改的三个地方:
phy_read(0x1): 0x0
phy_read(0x1): 0x0
phy_read(0x11): 0x0
operating at unknown: 0 mode
Using dm9000 device
dm9000_send: length: 42
dm9000_send: 00: ff ff ff ff ff ff 08 08
dm9000_send: 08: 11 18 12 27 08 06 00 01
dm9000_send: 10: 08 00 06 04 00 01 08 08
dm9000_send: 18: 11 18 12 27 c0 a8 00 02
dm9000_send: 20: 00 00 00 00 00 00 c0 a8
dm9000_send: 28: 00 10
transmit done
receiving packet
rx status: 0x0001 rx len: 64
dm9000_rx: length: 64
dm9000_rx: 00: 08 08 11 18 12 27 00 16
dm9000_rx: 08: ec 36 45 36 08 06 00 01
dm9000_rx: 10: 08 00 06 04 00 02 00 16
dm9000_rx: 18: ec 36 45 36 c0 a8 00 10
dm9000_rx: 20: 08 08 11 18 12 27 c0 a8
dm9000_rx: 28: 00 02 00 00 00 00 00 00
dm9000_rx: 30: 00 00 00 00 00 00 00 00
dm9000_rx: 38: 00 00 00 00 ea 5a 8c 9a
passing packet to upper layer
dm9000_send: length: 42
dm9000_send: 00: 00 16 ec 36 45 36 08 08
dm9000_send: 08: 11 18 12 27 08 00 45 00
dm9000_send: 10: 00 1c 00 01 40 00 ff 01
dm9000_send: 18: fa 7c c0 a8 00 02 c0 a8
dm9000_send: 20: 00 10 08 00 f7 fe 00 00
dm9000_send: 28: 00 01
transmit done
receiving packet
rx status: 0x0001 rx len: 64
dm9000_rx: length: 64
dm9000_rx: 00: 08 08 11 18 12 27 00 16
dm9000_rx: 08: ec 36 45 36 08 00 45 00
dm9000_rx: 10: 00 1c 39 18 40 00 40 01
dm9000_rx: 18: 80 66 c0 a8 00 10 c0 a8
dm9000_rx: 20: 00 02 00 00 ff fe 00 00
dm9000_rx: 28: 00 01 00 00 00 00 00 00
dm9000_rx: 30: 00 00 00 00 00 00 00 00
dm9000_rx: 38: 00 00 00 00 8f 46 5b ac
passing packet to upper layer
host 192.168.0.16 is alive
[u-boot@MINI2440]#
后记:细心的朋友也许会发现,这是tekkaman的作品,对,是他老人家的。我自己也修改了一个UBOOT,但是也PING不通,以为是我自己不细心造成的,所以就在网上下载了他老人家的,起到对比的作用。