Perl 截取文本中一段落

bobo5620301

// Generated for: spectre
// Generated on: May 16 11:15:28 2012
// Design library name: Genesis51xx
// Design cell name: DUV_Writer_Bravo
// Design view name: config
simulator lang=spectre
global 0 s_WriterOn!
parameters wbhv=0 vin_d=0.08125 vin_cm=1.8 trimVP12=0 trimVN12=0 trimIW=0 \
    trim14=0 t_rise=1e-10 t_on2=7 t_on=8.5e-05 t_off2=8 t_latch=-1 ssbb=0 \
    sel3=100 sel2=100 sel1=6 sel0=-1e-06 rhsel3=1 rhsel2=1 rhsel1=1 \
    rhsel0=1 rhdesel3=2 rhdesel2=2 rhdesel1=2 rhdesel0=2 preamble=0 \
    osbb_top=0 osbb_bot=0 oneT=1 maskLF=1 disOSonDeg=0 desel3=200 \
    desel2=200 desel1=9 desel0=0.000101 dc_sleep=0 dc_sel0=1 dc_on=1 \
    dcPol=1 _SmP=0 _STX=0 _IdealIc=1 _8V=1 _5V=0 _10V=0 Zmatch=3 Z=50 \
    WritePol=0 WdInOpenVth=0 Vios=0 VN30=-3 VCC=5 TrimVBG=5 TrimIABS=0 \
    Tpd=1e-07 SS_Delay=0 Rwdy=0.001 Rwdx=0.001 Rhead=3 RforOpen=0.001 \
    RforHSG=1000000000 RTC=0 PeclFlt=0 PPOffset=0 PC=0 OS_RTC=0 OS_Delay=0 \
    ODDurDac=1 NegHeadPol=0 MaxAmp=0 LowPwrWDI=0 LowPwrMUX=0 LowDataRate=0 \
    LinearDeg=0 Lhead=5e-10 IwDac=156 IosDac=130 InpBufFlt=0 ImodeGain=0 \
    I_oh_hs_test_Ena=0 HighVcm=0 FltEn=0 FTC=0 FOSDac=0 FOS=0 En_AB_Flt=0 \
    EnLoopBack=0 EnIndepDeg=0 EnHys=1 EnHCLFFault=0 EnDegaussTest=0 \
    EnDeg=1 EnAsym=0 DurDac=0 DisRTC_OS=0 DisODonDeg=1 DisOD=0 \
    DegFreqStop=0 DegFreqDiv=0 DegFreq=0 DegDur=3 DG_POL=0 DC_Degauss=0 \
    CpldFallEdge=0 Cpad=1 ChirpEn=0 ChannelDegauss=0 C2C_top=0 C2C_bot=0 \
    BmuxEnb=0 BitCellTime=5e-09 BankMuxEna=0 AmuxEnb=0 Amux=0 AC_output=0 \
    AC_input=0 ACVEE=0 ACVCC=0 ACErase=0 ABpwr=4 data_dur1=1e-08 \
    data_delay1=0.0002 IwDac_deg=IwDac IwDac2_deg=IwDac IwDac2=IwDac \
    IosDac_deg=IosDac IosDac2_deg=IosDac IosDac2=IosDac HyDegDur=DegDur \
    t_wake=t_on-5u data_dur=20*BitCellTime data_delay=t_on+500n \
    t_off=t_on+1u t_sleep=t_off+5u
include "$ICDS_CKTSIM_SW/lib/$ICDS_CKTSIM_TECH/sim/$CKTSIM_BRANCH/$ICDS_SIM_DATECODE/com3_sg.scs" section=c0
include "$PREAMP_CDS_INSTALL_PATH/etc/cdslib/artist/functional/allFunc.scs"
include "$ATC_MOUNT_PT/cds/common/$ICDS_TECH/sim/com3_sg_ov_vsbmax_fix.scs"

// Library name: GenSimAids
// Cell name: linear_1
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt linear_1 OUT VALUE VPOS
    V0 (V0_PLUS 0) vsource dc=900.0m type=dc
    E0 (vMSB 0 VALUE V0_PLUS) vcvs gain=10 min=0 max=1
    R9 (X0_out OUT) resistor r=100
    C12 (OUT 0) capacitor c=1p
    X0 (vMSB VPOS X0_out) f_multPli
ends linear_1
// End of subcircuit definition.

// Library name: GenSimAids
// Cell name: linear_2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt linear_2 OUT\<1\> OUT\<0\> VALUE VPOS

bobo5620301

MacBook-Pro:work bo$ cat got3.pl
#!/usr/bin/perl
# bobo5620301@163.com
open(IN,"/work/input.scs");
$count = 0;
$value = 0;

while(<IN>){

while (/^parameters\b/gi){
$value = 1;
}

while (/^include\b/gi){
$count = $count +1 ;
exit;
}


if ($value == 1 ){
print "$_";
}


}
close IN;