- 论坛徽章:
- 59
|
回复 6# wwwsq
to cpu, there are no difference between the 2/1 dim array.
in may case, the cache replacement policy are base on the actaul address of memory.
my english is poor, so , use the the following figure to descript what i means.
of course it is just a "as is" model (i use that the easiest understand model), not all cpu act like this.
the cpu cache are split into 128 byte blocks. the cache capacility is 128K, so that there are 1K cache lines available
+------+ cache line 1: 0~127
+------+ cache line 2: 128~255
+------+ cache line 3: 256~...
and the cache replacement policy is just use the following mapping function
aa= actual address
ca=cache line address
ca=aa&(1<<10+7) ; modeling to 128K ,the cache size
and if the cache not be hit, read one cache line arround the accessed memory.
then if the memory 0 be access: via code int a=*(int*)0;
and if the cpu found that the memory is not be hit in cache, cpu would load ((char*)0)[0...127] to cache line 0;
then the program may access the address around 0 such as 3,4,10,..., all the above may be found that they are allready stay in
the cache. so that the program may be speed up by caching.
so that if no memory access happen, nothing happened about the cache.
but if you do any accession of the memory , the cpu cache line may be changed(if this access is not hit the cache).
no worry about that you access object is the 2 or 1 dim of array, the caching policy can't understand what they are.
it just base on the memory address. (if no more complex cache memory policy applied) |
|
免费注册
楼主: wwwsq
发表于 2012-06-20 17:11
