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电梯直达

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发表于 2005-03-08 01:43 |只看该作者 |倒序浏览

有人私自改了nvalias, 现在连OBP也进不去了, 请各位大侠帮忙看看, 如何修复, 谢谢!!\r\n\r\nHardware Power ON\r\n\r\n@(#) Ultra Enterprise 3.2 Version 24 created 1999/12/23 17:31\r\nCPU = 0000.0000.0000.0000\r\nProbing keyboard Done\r\n\r\n0,0>;\r\n0,0>;@(#) POST 3.9.24 1999/12/23 17:35\r\n0,1>;\r\n0,0>;\r\n SelfTest Initializing (Diag Level 10, ENV 00004001) IMPL 0011 MASK 11\r\n0,1>;@(#) POST 3.9.24 1999/12/23 17:35\r\n0,0>;Board 0 CPU FPROM Test\r\n0,1>;\r\n SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK 11\r\n0,0>;Board 0 Basic CPU Test\r\n0,0>; Set CPU UPA Config and Init SDB Data\r\n0,0>; SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n0,0>;Board 0 MMU Enable Test\r\n0,0>; DMMU Init\r\n0,0>; IMMU Init\r\n0,0>; Mapping Selftest Enabling MMUs\r\n0,0>;Board 0 Ecache Test\r\n0,0>; Ecache Probe\r\n0,0>; Ecache Tags\r\n0,1>;Board 0 CPU FPROM Test\r\n0,1>;Board 0 Basic CPU Test\r\n0,1>; Set CPU UPA Config and Init SDB Data\r\n0,1>; SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0\r\n0,1>;Board 0 MMU Enable Test\r\n0,1>; DMMU Init\r\n0,1>; IMMU Init\r\n0,1>; Mapping Selftest Enabling MMUs\r\n0,1>;Board 0 Ecache Test\r\n0,1>; Ecache Probe\r\n0,1>; Ecache Tags\r\n0,0>; Ecache Quick Verify\r\n0,1>; Ecache Quick Verify\r\n0,0>; Ecache Init\r\n0,1>; Ecache Init\r\n0,0>; Ecache RAM\r\n0,0>; Ecache Address Line\r\n0,0>; Configure Ecache Limit\r\n0,0>;Ecache Size = 00100000, Limited to 00100000 \r\n0,0>;Board 0 FPU Functional Test\r\n0,0>; FPU Enable\r\n0,0>;Board 0 Board Master Select Test\r\n0,0>; Selecting a Board Master\r\n0,0>;Board 0 FireHose Devices Test\r\n0,1>; Ecache RAM\r\n0,1>; Ecache Address Line\r\n0,1>; Configure Ecache Limit\r\n0,1>;Ecache Size = 00100000, Limited to 00100000 \r\n0,1>;Board 0 FPU Functional Test\r\n0,1>; FPU Enable\r\n0,1>;Board 0 Board Master Select Test\r\n0,1>; Selecting a Board Master\r\n0,0>;Board 0 Address Controller Test\r\n0,0>; AC Initialization\r\n0,0>; AC DTAG Init\r\n0,0>;Board 0 Dual Tags Test\r\n0,0>; AC DTAG Init\r\n0,0>;Board 0 FireHose Controller Test\r\n0,0>; FHC Initialization\r\n0,0>;Board 0 JTAG Test\r\n0,0>; Verify System Board Scan Ring\r\n0,0>;Board 0 Centerplane Test\r\n0,0>; Centerplane Join\r\n0,0>;Setting JTAG Master\r\n0,0>;Clear JTAG Master\r\n0,0>;Board 0 Setup Cache Size Test\r\n0,0>; Setting Up Cache Size\r\n0,0>;Board 0 System Master Select Test\r\n0,0>; Setting System Master\r\n0,0>

OST Master Selected (JTAG,CENTRAL)\r\n0,0>;Board 16 Clock Board Test\r\n0,0>; Clock Board Initialization\r\n0,0>; Clock Board Temperature Check\r\n0,0>;Board 16 Clock Board Serial Ports Test\r\n0,0>;Board 16 NVRAM Devices Test\r\n0,0>; M48T59 (TOD) Init\r\n0,0>;Board 0 System Board Probe Test\r\n0,0>; Probing all CPU/Memory BDA\r\n0,0>; Probing System Boards\r\n0,0>; Probing CPU Module JTAG Rings\r\n0,0>;Setting System Clock Frequency\r\n0,0>; CPU Module mid 0 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 1 Version=00170011.11000507\r\n0,0>; CPU Module mid 1 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 4 Version=00170011.11000507\r\n0,0>; CPU Module mid 4 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 5 Version=00170011.11000507\r\n0,0>; CPU Module mid 5 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 8 Version=00170011.11000507\r\n0,0>; CPU Module mid 8 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 9 Version=00170011.11000507\r\n0,0>; CPU Module mid 9 Checked in OK (speed code = 4)\r\n0,0>; ******** Clock Reset - retesting \r\n0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496\r\n0,0>;\r\n0,0>;@(#) POST 3.9.24 1999/12/23 17:35\r\n0,1>;\r\n0,0>;\r\n SelfTest Initializing (Diag Level 40, ENV 00004081) IMPL 0011 MASK 11\r\n0,1>;@(#) POST 3.9.24 1999/12/23 17:35\r\n0,0>;Board 0 CPU FPROM Test\r\n0,1>;\r\n SelfTest Initializing (Diag Level 40, ENV 00004081) IMPL 0011 MASK 11\r\n0,0>; CPU/Memory Board FPROM Checksum Test\r\n0,1>;Board 0 CPU FPROM Test\r\n0,1>; CPU/Memory Board FPROM Checksum Test\r\n0,0>;Board 0 Basic CPU Test\r\n0,0>; FPU Registers and Data Path Test\r\n0,0>; Instruction Cache Tag RAM Test\r\n0,1>;Board 0 Basic CPU Test\r\n0,1>; FPU Registers and Data Path Test\r\n0,1>; Instruction Cache Tag RAM Test\r\n0,0>; Instruction Cache Instruction RAM Test\r\n0,1>; Instruction Cache Instruction RAM Test\r\n0,0>; Instruction Cache Next Field RAM Test\r\n0,1>; Instruction Cache Next Field RAM Test\r\n0,0>; Instruction Cache Pre-decode RAM Test\r\n0,1>; Instruction Cache Pre-decode RAM Test\r\n0,0>; Data Cache RAM Test\r\n0,1>; Data Cache RAM Test\r\n0,0>; Data Cache Tags Test\r\n0,1>; Data Cache Tags Test\r\n0,0>; DMMU Registers Access Test\r\n0,0>; DMMU TLB DATA RAM Access Test\r\n0,0>; DMMU TLB TAGS Access Test\r\n0,0>; IMMU Registers Access Test\r\n0,0>; IMMU TLB DATA RAM Access Test\r\n0,0>; IMMU TLB TAGS Access Test\r\n0,1>; DMMU Registers Access Test\r\n0,0>; Set CPU UPA Config and Init SDB Data\r\n0,0>; SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0\r\n0,1>; DMMU TLB DATA RAM Access Test\r\n0,0>;Board 0 MMU Enable Test\r\n0,0>; DMMU Init\r\n0,0>; IMMU Init\r\n0,0>; Mapping Selftest Enabling MMUs\r\n0,1>; DMMU TLB TAGS Access Test\r\n0,0>;Board 0 Ecache Test\r\n0,0>; Ecache Probe\r\n0,0>; Ecache Tags\r\n0,1>; IMMU Registers Access Test\r\n0,1>; IMMU TLB DATA RAM Access Test\r\n0,1>; IMMU TLB TAGS Access Test\r\n0,1>; Set CPU UPA Config and Init SDB Data\r\n0,1>; SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0\r\n0,1>;Board 0 MMU Enable Test\r\n0,1>; DMMU Init\r\n0,1>; IMMU Init\r\n0,1>; Mapping Selftest Enabling MMUs\r\n0,1>;Board 0 Ecache Test\r\n0,1>; Ecache Probe\r\n0,1>; Ecache Tags\r\n0,0>; Ecache Quick Verify\r\n0,0>; Ecache Init\r\n0,1>; Ecache Quick Verify\r\n0,1>; Ecache Init\r\n0,0>; Ecache RAM\r\n0,0>; Ecache 6N RAM Pattern Test\r\n0,1>; Ecache RAM\r\n0,0>; Ecache Address Line\r\n0,0>; Configure Ecache Limit\r\n0,0>;Ecache Size = 00100000, Limited to 00100000 \r\n0,1>; Ecache 6N RAM Pattern Test\r\n0,0>;Board 0 FPU Functional Test\r\n0,0>; FPU Enable\r\n0,0>;Board 0 Board Master Select Test\r\n0,0>; Selecting a Board Master\r\n0,0>;Board 0 FireHose Devices Test\r\n0,0>; PROM Datapath Test\r\n0,0>; FHC CPU SRAM Test\r\n0,1>; Ecache Address Line\r\n0,1>; Configure Ecache Limit\r\n0,1>;Ecache Size = 00100000, Limited to 00100000 \r\n0,1>;Board 0 FPU Functional Test\r\n0,1>; FPU Enable\r\n0,1>;Board 0 Board Master Select Test\r\n0,1>; Selecting a Board Master\r\n0,0>;Board 0 Address Controller Test\r\n0,0>; AC Registers Test\r\n0,0>; AC Initialization\r\n0,0>; Memory Registers Test\r\n0,0>; Memory Registers Initialization Test\r\n0,0>; AC DTAG Init\r\n0,0>;Board 0 Dual Tags Test\r\n0,0>; AC DTAG Test\r\n0,0>; AC DTAG Init\r\n0,0>;Board 0 FireHose Controller Test\r\n0,0>; FHC Initialization\r\n0,0>;Board 0 JTAG Test\r\n0,0>; Verify System Board Scan Ring\r\n0,0>;Board 0 Centerplane Test\r\n0,0>; Centerplane and Arbiter Check Test\r\n0,0>;Setting JTAG Master\r\n0,0>;Clear JTAG Master\r\n0,0>; Centerplane Join\r\n0,0>;Setting JTAG Master\r\n0,0>;Clear JTAG Master\r\n0,0>;Board 0 Setup Cache Size Test\r\n0,0>; Setting Up Cache Size\r\n0,0>;Board 0 System Master Select Test\r\n0,0>; Setting System Master\r\n0,0>

OST Master Selected (JTAG,CENTRAL)\r\n0,0>;Board 16 Clock Board Test\r\n0,0>; Clock Board Registers Test\r\n0,0>; Clock Board Initialization\r\n0,0>; Clock Board Temperature Check\r\n0,0>;Board 16 Clock Board Serial Ports Test\r\n0,0>; 85C30 Register Test\r\n0,0>; 85C30 Serial Ports Test\r\n0,0>; Keyboard Loopback\r\n0,0>; Mouse Loopback\r\n0,0>; Serial Port B Loopback\r\n0,0>; Remote Serial Port A Loopback\r\n0,0>; Remote Serial Port B Loopback\r\n0,0>;Board 16 NVRAM Devices Test\r\n0,0>; M48T59 (TOD) Init\r\n0,0>; M48T59 (TOD) Functional Part 1 Test\r\n0,0>; NVRAM(Non-Destructive) Test\r\n0,0>;Board 0 System Board Probe Test\r\n0,0>; Probing all CPU/Memory BDA\r\n0,0>; Probing System Boards\r\n0,0>; Probing CPU Module JTAG Rings\r\n0,0>;Setting System Clock Frequency\r\n0,0>; CPU Module mid 0 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 1 Version=00170011.11000507\r\n0,0>; CPU Module mid 1 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 4 Version=00170011.11000507\r\n0,0>; CPU Module mid 4 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 5 Version=00170011.11000507\r\n0,0>; CPU Module mid 5 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 8 Version=00170011.11000507\r\n0,0>; CPU Module mid 8 Checked in OK (speed code = 4)\r\n0,0>; CPU mid 9 Version=00170011.11000507\r\n0,0>; CPU Module mid 9 Checked in OK (speed code = 4)\r\n0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496\r\n0,0>;TESTING BOARD 1\r\n0,0>;Board 1 JTAG Test\r\n0,0>; Verify System Board Scan Ring\r\n0,0>;Board 1 Centerplane Test\r\n0,0>; Centerplane Check\r\n0,0>;Board 1 Address Controller Test\r\n0,0>; AC Registers Test\r\n0,0>; AC Initialization\r\n0,0>;Setting Freq to 25MHZ\r\n0,0>; Memory Registers Test\r\n0,0>; Memory Registers Initialization Test\r\n0,0>; AC DTAG Init\r\n0,0>;Board 1 FireHose Controller Test\r\n0,0>; FHC Initialization\r\n0,0>;Board 1 NVRAM Devices Test\r\n0,0>; M48T59 (TOD) Init\r\n0,0>; M48T59 (TOD) Functional Part 1 Test\r\n0,0>; NVRAM(Non-Destructive) Test\r\n0,0>;TESTING BOARD 6\r\n0,0>;Board 6 JTAG Test\r\n0,0>; Verify System Board Scan Ring\r\n0,0>;Board 6 Centerplane Test\r\n0,0>; Centerplane Check\r\n0,0>;Board 6 Address Controller Test\r\n0,0>; AC Registers Test\r\n0,0>; AC Initialization\r\n0,0>;Setting Freq to 25MHZ\r\n0,0>; Memory Registers Test\r\n0,0>; Memory Registers Initialization Test\r\n0,0>; AC DTAG Init\r\n0,0>;Board 6 FireHose Controller Test\r\n0,0>; FHC Initialization\r\n0,0>;Board 6 NVRAM Devices Test\r\n0,0>; M48T59 (TOD) Init\r\n0,0>; M48T59 (TOD) Functional Part 1 Test\r\n0,0>; NVRAM(Non-Destructive) Test\r\n0,0>;Re-mapping to Local Device Space\r\n0,0>;Begin Central Space Serial Port access\r\n0,0>;Enable AC Control Parity\r\n0,0>;Hotplug Trigger Test\r\n0,0>;Init Counters for Hotplug\r\n0,0>;Board 0 Cross Calls Test\r\n0,0>; Cross Calls Test\r\n0,0>;Displaying PROM Versions\r\n0,0>;Slot 0 CPU/Memory OBP 3.2.24 1999/12/23 17:31 POST 3.9.24 1999/12/23 17:35\r\n0,0>;Slot 1 IO Type 1 FCODE 1.8.24 1999/12/23 17:29 iPOST 3.4.24 1999/12/23 17:34\r\n0,0>;Slot 2 CPU/Memory OBP 3.2.24 1999/12/23 17:31 POST 3.9.24 1999/12/23 17:35\r\n0,0>;Slot 4 CPU/Memory OBP 3.2.24 1999/12/23 17:31 POST 3.9.24 1999/12/23 17:35\r\n0,0>;Slot 6 IO Type 1 FCODE 1.8.24 1999/12/23 17:29 iPOST 3.4.24 1999/12/23 17:34\r\n0,0>;Board 0 Environmental Probe Test\r\n0,0>; Environmental Probe\r\n0,0>;Checking Power Supply Configuration\r\n0,0>

ower is more than adequate, load 5 ps 4\r\n0,0>;Reconfig memory due to POR or CLOCK RESET\r\n0,0>;Reconfig memory due to DIAG_LEVEL\r\n0,0>;Board 0 Probing Memory SIMMS Test\r\n0,0>; Probe SIMMID\r\n0,0>; Populated Memory Bank Status\r\n0,0>; bd # Size Address Way Status\r\n0,0>; 0 256 Normal\r\n0,0>; 0 256 Normal\r\n0,0>; 2 256 Normal\r\n0,0>; 2 256 Normal\r\n0,0>; 4 256 Normal\r\n0,0>; 4 256 Normal\r\n0,0>;Board 0 Memory Configuration Test\r\n0,0>; Memory Interleaving\r\n0,0>; Total banks with 8MB SIMMs = 0\r\n0,0>; Total banks with 32MB SIMMs = 6\r\n0,0>; Total banks with 128MB SIMMs = 0\r\n0,0>; Total banks with 256MB SIMMs = 0\r\n0,0>; Overall memory default speed = 60ns\r\n0,0>;Do OPTIMAL INTLV\r\n0,0>; Board 0 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Board 2 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Board 4 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Board 0 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Board 2 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Board 4 AC rev 5 RCTIME = 0 (Tras 71)\r\n0,0>; Memory Refresh Enable\r\n0,0>;Board 0 SIMMs Test\r\n0,0>; MP Memory SIMM Clear Test\r\n0,0>; Memory Size is 1536Mbytes\r\n0,0>; CPU MID 1 clearing 00000000.00004000 to 00000000.10000000\r\n0,0>; CPU MID 4 clearing 00000000.10000000 to 00000000.20000000\r\n0,0>; CPU MID 5 clearing 00000000.20000000 to 00000000.30000000\r\n0,0>; CPU MID 8 clearing 00000000.30000000 to 00000000.40000000\r\n0,0>; CPU MID 9 clearing 00000000.40000000 to 00000000.50000000\r\n0,0>; CPU MID 0 clearing 00000000.50000000 to 00000000.60000000\r\n0,0>; CPU MID 0 clearing 00000000.00000000 to 00000000.00004000\r\n0,0>; Memory Walking Rows and Columns Test\r\n0,0>; MP Memory SIMM (6N RAM Patterns) Test\r\n0,0>; Memory Size is 1536Mbytes\r\n0,0>; CPU MID 1 testing 00000000.00000000 to 00000000.10000000\r\n0,0>; CPU MID 4 testing 00000000.10000000 to 00000000.20000000\r\n0,0>; CPU MID 5 testing 00000000.20000000 to 00000000.30000000\r\n0,0>; CPU MID 8 testing 00000000.30000000 to 00000000.40000000\r\n0,0>; CPU MID 9 testing 00000000.40000000 to 00000000.50000000\r\n0,0>; CPU MID 0 testing 00000000.50000000 to 00000000.60000000\r\n0,0>; MP Memory SIMM (moving inverse) Test\r\n0,0>; Memory Size is 1536Mbytes\r\n0,0>; CPU MID 1 testing 00000000.00000000 to 00000000.10000000\r\n0,0>; CPU MID 4 testing 00000000.10000000 to 00000000.20000000\r\n0,0>; CPU MID 5 testing 00000000.20000000 to 00000000.30000000\r\n0,0>; CPU MID 8 testing 00000000.30000000 to 00000000.40000000\r\n0,0>; CPU MID 9 testing 00000000.40000000 to 00000000.50000000\r\n0,0>; CPU MID 0 testing 00000000.50000000 to 00000000.60000000\r\n0,0>;Slave CPU Functional Tests\r\n0,0>; Slave CPU MID 1 started\r\n0,1>;Board 0 Functional CPU 1 Test\r\n0,1>; Dcache Init\r\n0,1>; Dcache Enable Test\r\n0,1>; Dcache Functionality Test\r\n0,1>; Ecache Stress Test\r\n0,1>; Ecache Functional Test\r\n0,1>; CPU Dispatch (Multi-Scalar) Test\r\n0,1>; SPARC Atomic Instructions Test\r\n0,1>; SPARC Prefetch Instructions Test\r\n0,1>; CPU Softint Registers and Interrupts Test\r\n0,1>; Uni-Processor Cache Coherence Test\r\n0,1>; Branch Memory Test\r\n0,1>; SDB ECC CE Test\r\n0,1>; SDB ECC Uncorrectable Test\r\n0,1>; FPU Instruction Test\r\n0,0>; Slave CPU MID 4 started\r\n2,0>;Board 2 Functional CPU 0 Test\r\n2,0>; Dcache Init\r\n2,0>; Dcache Enable Test\r\n2,0>; Dcache Functionality Test\r\n2,0>; Ecache Stress Test\r\n2,0>; Ecache Functional Test\r\n2,0>; CPU Dispatch (Multi-Scalar) Test\r\n2,0>; SPARC Atomic Instructions Test\r\n2,0>; SPARC Prefetch Instructions Test\r\n2,0>; CPU Softint Registers and Interrupts Test\r\n2,0>; Uni-Processor Cache Coherence Test\r\n2,0>; Branch Memory Test\r\n2,0>; SDB ECC CE Test\r\n2,0>; SDB ECC Uncorrectable Test\r\n2,0>; FPU Instruction Test\r\n0,0>; Slave CPU MID 5 started\r\n2,1>;Board 2 Functional CPU 1 Test\r\n2,1>; Dcache Init\r\n2,1>; Dcache Enable Test\r\n2,1>; Dcache Functionality Test\r\n2,1>; Ecache Stress Test\r\n2,1>; Ecache Functional Test\r\n2,1>; CPU Dispatch (Multi-Scalar) Test\r\n2,1>; SPARC Atomic Instructions Test\r\n2,1>; SPARC Prefetch Instructions Test\r\n2,1>; CPU Softint Registers and Interrupts Test\r\n2,1>; Uni-Processor Cache Coherence Test\r\n2,1>; Branch Memory Test\r\n2,1>; SDB ECC CE Test\r\n2,1>; SDB ECC Uncorrectable Test\r\n2,1>; FPU Instruction Test\r\n0,0>; Slave CPU MID 8 started\r\n4,0>;Board 4 Functional CPU 0 Test\r\n4,0>; Dcache Init\r\n4,0>; Dcache Enable Test\r\n4,0>; Dcache Functionality Test\r\n4,0>; Ecache Stress Test\r\n4,0>; Ecache Functional Test\r\n4,0>; CPU Dispatch (Multi-Scalar) Test\r\n4,0>; SPARC Atomic Instructions Test\r\n4,0>; SPARC Prefetch Instructions Test\r\n4,0>; CPU Softint Registers and Interrupts Test\r\n4,0>; Uni-Processor Cache Coherence Test\r\n4,0>; Branch Memory Test\r\n4,0>; SDB ECC CE Test\r\n4,0>; SDB ECC Uncorrectable Test\r\n4,0>; FPU Instruction Test\r\n0,0>; Slave CPU MID 9 started\r\n4,1>;Board 4 Functional CPU 1 Test\r\n4,1>; Dcache Init\r\n4,1>; Dcache Enable Test\r\n4,1>; Dcache Functionality Test\r\n4,1>; Ecache Stress Test\r\n4,1>; Ecache Functional Test\r\n4,1>; CPU Dispatch (Multi-Scalar) Test\r\n4,1>; SPARC Atomic Instructions Test\r\n4,1>; SPARC Prefetch Instructions Test\r\n4,1>; CPU Softint Registers and Interrupts Test\r\n4,1>; Uni-Processor Cache Coherence Test\r\n4,1>; Branch Memory Test\r\n4,1>; SDB ECC CE Test\r\n4,1>; SDB ECC Uncorrectable Test\r\n4,1>; FPU Instruction Test\r\n0,0>;Board 0 Functional CPU 0 Test\r\n0,0>; Dcache Init\r\n0,0>; Dcache Enable Test\r\n0,0>; Dcache Functionality Test\r\n0,0>; Ecache Stress Test\r\n0,0>; Ecache Functional Test\r\n0,0>; CPU Dispatch (Multi-Scalar) Test\r\n0,0>; SPARC Atomic Instructions Test\r\n0,0>; SPARC Prefetch Instructions Test\r\n0,0>; CPU Softint Registers and Interrupts Test\r\n0,0>; Uni-Processor Cache Coherence Test\r\n0,0>; Branch Memory Test\r\n0,0>; SDB ECC CE Test\r\n0,0>; SDB ECC Uncorrectable Test\r\n0,0>; FPU Instruction Test\r\n0,0>;TESTING IO BOARD 1\r\n0,0>;Board 1 I/O FPROM Test\r\n0,0>; I/O Board EPROM checksum Test\r\n0,0>;@(#) iPOST 3.4.24 1999/12/23 17:34\r\n0,0>; TESTING IO BOARD 1 ASICs\r\n0,0>; TESTING SysIO Port 0\r\n0,0>;Board 1 SysIO Registers Test\r\n0,0>; SysIO Register Initialization\r\n0,0>; IOMMU Registers and RAM Test\r\n0,0>; Streaming Buffer Registers and RAM Test\r\n0,0>; SBus Control and Config Registers Test\r\n0,0>; SysIO RAM Initialization\r\n0,0>;Board 1 SysIO Functional Test\r\n0,0>; Clear Interrupt Map and State Registers\r\n0,0>; SysIO Interrupts Test\r\n0,0>; SysIO Timers/Counters Test\r\n0,0>; IOMMU Virtual Address TLB Tag Compare Test\r\n0,0>; Streaming Buffer Flush Test\r\n0,0>; DMA Merge Buffer Test\r\n0,0>; SYSIO ECC Correctable Test\r\n0,0>; SYSIO ECC UnCorrectable Test\r\n0,0>; SysIO Sbus Probe Test\r\n0,0>; Sbus Card Installed, slot #1, addr 000001c5.10000000\r\n0,0>; Sbus Card Installed, slot #2, addr 000001c5.20000000\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;Board 1 OnBoard IO Chipset (SOC) Test\r\n0,0>; SOC SRAM Test\r\n0,0>; SOC Registers Test\r\n0,0>; SOC Interrupt Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>; TESTING SysIO Port 1\r\n0,0>;Board 1 SysIO Registers Test\r\n0,0>; SysIO Register Initialization\r\n0,0>; IOMMU Registers and RAM Test\r\n0,0>; Streaming Buffer Registers and RAM Test\r\n0,0>; SBus Control and Config Registers Test\r\n0,0>; SysIO RAM Initialization\r\n0,0>;Board 1 SysIO Functional Test\r\n0,0>; Clear Interrupt Map and State Registers\r\n0,0>; SysIO Interrupts Test\r\n0,0>; SysIO Timers/Counters Test\r\n0,0>; IOMMU Virtual Address TLB Tag Compare Test\r\n0,0>; Streaming Buffer Flush Test\r\n0,0>; DMA Merge Buffer Test\r\n0,0>; SYSIO ECC Correctable Test\r\n0,0>; SYSIO ECC UnCorrectable Test\r\n0,0>; SysIO Sbus Probe Test\r\n0,0>; Sbus Card Installed, slot #0, addr 000001c7.00000000\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;Board 1 OnBoard IO Chipset (FEPS) Test\r\n0,0>; FAS366 Registers Test\r\n0,0>; ESP FAS366 DVMA burst mode read/write Test\r\n0,0>; FAS366 FIFO TO DMA Test\r\n0,0>; DMA TO FAS366 FIFO Test\r\n0,0>; FEPS (Ethernet) Registers Test\r\n0,0>; FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;IO BOARD 1 TESTED\r\n0,0>;TESTING IO BOARD 6\r\n0,0>;Board 6 I/O FPROM Test\r\n0,0>; I/O Board EPROM checksum Test\r\n0,0>;@(#) iPOST 3.4.24 1999/12/23 17:34\r\n0,0>; TESTING IO BOARD 6 ASICs\r\n0,0>; TESTING SysIO Port 0\r\n0,0>;Board 6 SysIO Registers Test\r\n0,0>; SysIO Register Initialization\r\n0,0>; IOMMU Registers and RAM Test\r\n0,0>; Streaming Buffer Registers and RAM Test\r\n0,0>; SBus Control and Config Registers Test\r\n0,0>; SysIO RAM Initialization\r\n0,0>;Board 6 SysIO Functional Test\r\n0,0>; Clear Interrupt Map and State Registers\r\n0,0>; SysIO Interrupts Test\r\n0,0>; SysIO Timers/Counters Test\r\n0,0>; IOMMU Virtual Address TLB Tag Compare Test\r\n0,0>; Streaming Buffer Flush Test\r\n0,0>; DMA Merge Buffer Test\r\n0,0>; SYSIO ECC Correctable Test\r\n0,0>; SYSIO ECC UnCorrectable Test\r\n0,0>; SysIO Sbus Probe Test\r\n0,0>; SBus Card not Installed, slot 1 addr 000001d9.10000000\r\n0,0>; Sbus Card Installed, slot #2, addr 000001d9.20000000\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;Board 6 OnBoard IO Chipset (SOC) Test\r\n0,0>; SOC SRAM Test\r\n0,0>; SOC Registers Test\r\n0,0>; SOC Interrupt Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>; TESTING SysIO Port 1\r\n0,0>;Board 6 SysIO Registers Test\r\n0,0>; SysIO Register Initialization\r\n0,0>; IOMMU Registers and RAM Test\r\n0,0>; Streaming Buffer Registers and RAM Test\r\n0,0>; SBus Control and Config Registers Test\r\n0,0>; SysIO RAM Initialization\r\n0,0>;Board 6 SysIO Functional Test\r\n0,0>; Clear Interrupt Map and State Registers\r\n0,0>; SysIO Interrupts Test\r\n0,0>; SysIO Timers/Counters Test\r\n0,0>; IOMMU Virtual Address TLB Tag Compare Test\r\n0,0>; Streaming Buffer Flush Test\r\n0,0>; DMA Merge Buffer Test\r\n0,0>; SYSIO ECC Correctable Test\r\n0,0>; SYSIO ECC UnCorrectable Test\r\n0,0>; SysIO Sbus Probe Test\r\n0,0>; SBus Card not Installed, slot 0 addr 000001db.00000000\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;Board 6 OnBoard IO Chipset (FEPS) Test\r\n0,0>; FAS366 Registers Test\r\n0,0>; ESP FAS366 DVMA burst mode read/write Test\r\n0,0>; FAS366 FIFO TO DMA Test\r\n0,0>; DMA TO FAS366 FIFO Test\r\n0,0>; FEPS (Ethernet) Registers Test\r\n0,0>; FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test\r\n0,0>; SysIO Register Initialization Test\r\n0,0>; SysIO RAM Initialization Test\r\n0,0>; Clear Interrupt Map and State Registers Test\r\n0,0>;IO BOARD 6 TESTED\r\n0,0>;SYSTEM LEVEL TESTING\r\n0,0>;Board 0 Cache Coherency Test\r\n0,0>; Multi-Processor Cache Coherence Test\r\n0,0>; Testing CPU MID 1\r\n0,0>; Testing CPU MID 4\r\n0,0>; Testing CPU MID 5\r\n0,0>; Testing CPU MID 8\r\n0,0>; Testing CPU MID 9\r\n0,0>

robing for Disk System boards\r\n0,0>;Board 0 System Interrupts Test\r\n0,0>; System Interrupts Test\r\n0,0>;Checking Power Supply Configuration\r\n0,0>

ower is more than adequate, load 5 ps 4\r\n0,0>; Check Board Present Test\r\n0,0>; Board Present Interrupt Test\r\n0,0>;\r\n0,0>; System Board Status\r\n0,0>;-----------------------------------------------------------------\r\n0,0>; Slot Board Status Board Type Failures\r\n0,0>;-----------------------------------------------------------------\r\n0,0>; 0 | Normal | CPU/Memory |\r\n0,0>; 1 | Normal | IO Type 1 |\r\n0,0>; 2 | Normal | CPU/Memory |\r\n0,0>; 3 | Normal | Disk Board |\r\n0,0>; 4 | Normal | CPU/Memory |\r\n0,0>; 5 | Normal | Disk Board |\r\n0,0>; 6 | Normal | IO Type 1 |\r\n0,0>; 7 | Normal | Disk Board |\r\n0,0>; 16 | Normal | Clock Board |\r\n0,0>;-----------------------------------------------------------------\r\n0,0>;\r\n0,0>; CPU Module Status\r\n0,0>;-----------------------------------------------------------------\r\n0,0>; MID OK Cache Speed Version\r\n0,0>;-----------------------------------------------------------------\r\n0,0>; 0 | y | 1024 | 248 | 00170011.11000507\r\n0,0>; 1 | y | 1024 | 248 | 00170011.11000507\r\n0,0>; 4 | y | 1024 | 248 | 00170011.11000507\r\n0,0>; 5 | y | 1024 | 248 | 00170011.11000507\r\n0,0>; 8 | y | 1024 | 248 | 00170011.11000507\r\n0,0>; 9 | y | 1024 | 248 | 00170011.11000507\r\n0,0>;-----------------------------------------------------------------\r\n0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496\r\n0,0>; Populated Memory Bank Status\r\n0,0>; bd # Size Address Way Status\r\n0,0>; 0 256 0 4 Normal\r\n0,0>; 0 256 3 4 Normal\r\n0,0>; 2 256 1 4 Normal\r\n0,0>; 2 256 0 2 Normal\r\n0,0>; 4 256 2 4 Normal\r\n0,0>; 4 256 1 2 Normal\r\n0,0>;\r\n0,0>; Disk Board Status\r\n0,0>;-----------------------------------------------------------------\r\n0,0>;Slot Sckt0 Sckt1\r\n0,0>;-----------------------------------------------------------------\r\n0,0>; 3 Disk10 Disk11\r\n0,0>;\r\n0,0>; 5 Disk12 Disk13\r\n0,0>;\r\n0,0>; 7 Disk14 Disk15\r\n0,0>;\r\n0,0>;\r\n0,0>;\r\n POST COMPLETE\r\n0,0>;Entering OBP\r\n\r\nSwitching to high addresses \r\nSetting up TLBs Done\r\nMMU ON\r\nPC = 0000.01ff.f000.1cb8\r\nPC = 0000.0000.0000.1d24\r\nDecompressing in Memory Done\r\nSize = 0000.0000.0007.01d0\r\nttya initialized\r\nUsing POST\'s System Configuration\r\nSetting up memory\r\nStarting CPU ID 1 \r\nStarting CPU ID 4 \r\nStarting CPU ID 5 \r\nStarting CPU ID 8 \r\nStarting CPU ID 9 \r\nClock board TOD does not match TOD on any IO board.\r\nfhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II \r\nfhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II \r\nfhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II \r\ndisk-board disk-board disk-board \r\nProbing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer \r\nProbing UPA Slot at 3,0 sbus counter-timer \r\nProbing UPA Slot at c,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer \r\nProbing UPA Slot at d,0 sbus counter-timer \r\nProbing /sbus@2,0 at d,0 SUNW,soc \r\nProbing /sbus@2,0 at 1,0 SUNW,socal sf ssd sf ssd \r\nProbing /sbus@2,0 at 2,0 SUNW,socal sf ssd sf ssd \r\nProbing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st \r\nProbing /sbus@3,0 at 0,0 cgsix \r\nProbing /sbus@c,0 at d,0 SUNW,soc \r\nProbing /sbus@c,0 at 1,0 Nothing there\r\nProbing /sbus@c,0 at 2,0 SUNW,socal sf ssd sf ssd \r\nProbing /sbus@d,0 at 3,0 SUNW,hme SUNW,fas sd st \r\nProbing /sbus@d,0 at 0,0 Nothing there