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v440最大化自检到这里就进行不下去了系统起不来求故障位置是哪里 [复制链接]

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发表于 2013-04-08 10:04 |只看该作者 |倒序浏览

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1>Init CPU
2>Init CPU
3>Init CPU
1>    UltraSPARC[TM] IIIi, Version 3.4
2>    UltraSPARC[TM] IIIi, Version 3.4
3>    UltraSPARC[TM] IIIi, Version 3.4

******  POST Running ******

1>DMMU
2>DMMU
3>DMMU
1>DMMU TLB DATA RAM Access
2>DMMU TLB DATA RAM Access
3>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
2>DMMU TLB TAGS Access
3>DMMU TLB TAGS Access
1>IMMU Registers Access
2>IMMU Registers Access
3>IMMU Registers Access
1>IMMU TLB DATA RAM Access
2>IMMU TLB DATA RAM Access
3>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
2>IMMU TLB TAGS Access
3>IMMU TLB TAGS Access
1>Init mmu regs
2>Init mmu regs
3>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>    Size = 00000000.00100000...
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2>    Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3>    Size = 00000000.00100000...
1>Scrub and Setup L2 Cache
2>Scrub and Setup L2 Cache
3>Scrub and Setup L2 Cache
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Test  Mailbox
2>Test  Mailbox
3>Test  Mailbox
1>Scrub Mailbox
2>Scrub Mailbox
3>Scrub Mailbox
1>CPU Tick and Tick Compare Registers Test
2>CPU Tick and Tick Compare Registers Test
3>CPU Tick and Tick Compare Registers Test
1>CPU Stick and Stick Compare Registers Test
2>CPU Stick and Stick Compare Registers Test
3>CPU Stick and Stick Compare Registers Test
1>Setup Int Handlers
2>Setup Int Handlers
3>Setup Int Handlers
0>Interrupt Crosscall.....
0>Setup Int Handlers
0>Send Int CPU 1
0>Send Int CPU 2
0>Send Int CPU 3
1>Send Int to Master CPU
2>Send Int to Master CPU
3>Send Int to Master CPU
0>MB: Part-Dash-Rev#:  5016910-01-50  Serial#:  033264
0>CPU0: Part-Dash-Rev#:  5017029-03-51  Serial#:  060361
0>CPU1: Part-Dash-Rev#:  5017029-03-51  Serial#:  060360
0>CPU2: Part-Dash-Rev#:  5017029-03-51  Serial#:  060356
0>CPU3: Part-Dash-Rev#:  5017029-03-51  Serial#:  060359
0>Set CPU/System Speed
0>........
0>Send MC Timing CPU 1
0>Send MC Timing CPU 2
0>Send MC Timing CPU 3
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
2>Probe Dimms
3>Probe Dimms
1>Init Mem Controller Regs
2>Init Mem Controller Regs
3>Init Mem Controller Regs
0>Init Mem Controller Regs
1>Set JBUS config reg
2>Set JBUS config reg
3>Set JBUS config reg
0>Set JBUS config reg
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Do PLL reset
0>Setting timing to 7:1 10:1, system frequency 183 MHz, CPU frequency 1281 MHz

SC Alert: Host System has Reset
0>Soft Power-on RST thru SW
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>    Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 7:1 10:1, sys 183 MHz, CPU 1281 MHz, mem 128 MHz.
0>    UltraSPARC[TM] IIIi, Version 3.4
1>Init CPU
2>Init CPU
3>Init CPU
1>    UltraSPARC[TM] IIIi, Version 3.4
2>    UltraSPARC[TM] IIIi, Version 3.4
3>    UltraSPARC[TM] IIIi, Version 3.4
1>Init mmu regs
2>Init mmu regs
3>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>    Size = 00000000.00100000...
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2>    Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3>    Size = 00000000.00100000...
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Scrub Mailbox
2>Scrub Mailbox
3>Scrub Mailbox
1>Timing is 7:1 10:1, sys 183 MHz, CPU 1281 MHz, mem 128 MHz.
2>Timing is 7:1 10:1, sys 183 MHz, CPU 1281 MHz, mem 128 MHz.
3>Timing is 7:1 10:1, sys 183 MHz, CPU 1281 MHz, mem 128 MHz.
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
2>Probe Dimms
3>Probe Dimms
1>Init Mem Controller Sequence
2>Init Mem Controller Sequence
3>Init Mem Controller Sequence
0>Init Mem Controller Sequence
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 1024MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: 1024MB Bank 2, Dimm Type X4
0>INFO: No memory detected in Bank 3
0>
0>Data Bitwalk on Master
0>    Test Bank 0.
0>    Test Bank 2.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000.
0>Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.40000000.
0>Set Mailbox
0>Final mc1 is 30000026.3e781c4e.
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
2>Waiting for master CPU=0, timeout in 179 seconds...
1>Waiting for master CPU=0, timeout in 179 seconds...
3>Waiting for master CPU=0, timeout in 179 seconds...
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 14ed.
0>The Memory's Content Size value is 99a21.
0>Success...  Checksum on Memory Validated.
1>Select Bank Config
2>Select Bank Config
3>Select Bank Config
1>Probe and Setup Memory
1>INFO: 1024MB Bank 0, Dimm Type X4
1>INFO: No memory detected in Bank 1
1>INFO: 1024MB Bank 2, Dimm Type X4
1>INFO: No memory detected in Bank 3
1>
2>Probe and Setup Memory
2>INFO: 1024MB Bank 0, Dimm Type X4
2>INFO: No memory detected in Bank 1
2>INFO: 1024MB Bank 2, Dimm Type X4
2>INFO: No memory detected in Bank 3
2>
3>Probe and Setup Memory
3>INFO: 1024MB Bank 0, Dimm Type X4
3>INFO: No memory detected in Bank 1
3>INFO: 1024MB Bank 2, Dimm Type X4
3>INFO: No memory detected in Bank 3
3>
1>Set Mailbox
2>Set Mailbox
3>Set Mailbox
1>Final mc1 is 30000026.3e781c4e.
2>Final mc1 is 30000026.3e781c4e.
3>Final mc1 is 30000026.3e781c4e.
0>Data Bitwalk on Slave 1
0>    Test Bank 0.
0>    Test Bank 2.
0>Data Bitwalk on Slave 2
0>    Test Bank 0.
0>    Test Bank 2.
0>Data Bitwalk on Slave 3
0>    Test Bank 0.
0>    Test Bank 2.
0>Address Bitwalk on Slave 1
0>Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.40000000.
0>Addr walk mem test on CPU 1 Bank 2: 00000012.00000000 to 00000012.40000000.
0>Address Bitwalk on Slave 2
0>Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.40000000.
0>Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.40000000.
0>Address Bitwalk on Slave 3
0>Addr walk mem test on CPU 3 Bank 0: 00000030.00000000 to 00000030.40000000.
0>Addr walk mem test on CPU 3 Bank 2: 00000032.00000000 to 00000032.40000000.
1>Setup Final DMMU Entries
2>Setup Final DMMU Entries
3>Setup Final DMMU Entries
1>Map Slave POST to master memory
2>Map Slave POST to master memory
3>Map Slave POST to master memory
1>FPU Registers and Data Path
2>FPU Registers and Data Path
3>FPU Registers and Data Path
0>FPU Registers and Data Path
1>FPU Move Registers
2>FPU Move Registers
3>FPU Move Registers
0>FPU Move Registers
1>FSR Read/Write
2>FSR Read/Write
3>FSR Read/Write
0>FSR Read/Write
1>FPU Block Register Test
2>FPU Block Register Test
3>FPU Block Register Test
0>FPU Block Register Test
1>Scrub Memory
2>Scrub Memory
3>Scrub Memory
0>Scrub Memory
1>Quick Block Mem Test
1>Quick Test 4194304 bytes at 00000010.00000000
2>Quick Block Mem Test
2>Quick Test 4194304 bytes at 00000020.00000000
0>Quick Block Mem Test
0>Quick Test 4194304 bytes at 00000000.00600000
3>Quick Block Mem Test
3>Quick Test 4194304 bytes at 00000030.00000000
1>Quick Test 4194304 bytes at 00000012.00000000
2>Quick Test 4194304 bytes at 00000022.00000000
0>Quick Test 4194304 bytes at 00000002.00000000
3>Quick Test 4194304 bytes at 00000032.00000000
1>Flush Caches
2>Flush Caches
3>Flush Caches
0>Flush Caches
0>XBus SRAM
0>IO-Bridge SouthBridge Remap Devs
0>IO-Bridge Tests.....
0>JBUS quick check
0>    to IO-bridge_0
0>    to IO-bridge_1
0>IO-Bridge unit 0 sram    test
0>IO-Bridge unit 0 reg    test
0>IO-Bridge unit 0 mem    test
0>IO-Bridge unit 0 PCI id test
0>IO-Bridge unit 0 interrupt test
0>IO-Bridge unit 1 sram    test
0>IO-Bridge unit 1 reg    test
0>IO-Bridge unit 1 mem    test
0>IO-Bridge unit 1 PCI id test
0>IO-Bridge unit 1 interrupt test
0>IO-Bridge unit 0 init    test
1>IO-Bridge unit 0 sram    test
1>IO-Bridge unit 0 reg    test
1>IO-Bridge unit 0 mem    test
1>IO-Bridge unit 0 PCI id test
1>IO-Bridge unit 0 interrupt test
1>IO-Bridge unit 1 init    test
1>IO-Bridge unit 1 sram    test
1>IO-Bridge unit 1 reg    test
1>IO-Bridge unit 1 mem    test
1>IO-Bridge unit 1 PCI id test
1>IO-Bridge unit 1 interrupt test
1>IO-Bridge unit 0 init    test
2>IO-Bridge unit 0 sram    test
2>IO-Bridge unit 0 reg    test
2>IO-Bridge unit 0 mem    test
2>IO-Bridge unit 0 PCI id test
2>IO-Bridge unit 0 interrupt test
2>IO-Bridge unit 1 init    test
2>IO-Bridge unit 1 sram    test
2>IO-Bridge unit 1 reg    test
2>IO-Bridge unit 1 mem    test
2>IO-Bridge unit 1 PCI id test
2>IO-Bridge unit 1 interrupt test
2>IO-Bridge unit 0 init    test
3>IO-Bridge unit 0 sram    test
3>IO-Bridge unit 0 reg    test
3>IO-Bridge unit 0 mem    test
3>IO-Bridge unit 0 PCI id test
3>IO-Bridge unit 0 interrupt test
3>IO-Bridge unit 1 init    test
3>IO-Bridge unit 1 sram    test
3>IO-Bridge unit 1 reg    test
3>IO-Bridge unit 1 mem    test
3>IO-Bridge unit 1 PCI id test
3>IO-Bridge unit 1 interrupt test
3>Print Mem Config
1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1>Memory interleave set to 0
1>    Bank 0 1024MB : 00000010.00000000 -> 00000010.3fffffff.
1>    Bank 2 1024MB : 00000012.00000000 -> 00000012.3fffffff.
2>Print Mem Config
2>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2>Memory interleave set to 0
2>    Bank 0 1024MB : 00000020.00000000 -> 00000020.3fffffff.
2>    Bank 2 1024MB : 00000022.00000000 -> 00000022.3fffffff.
3>Print Mem Config
3>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3>Memory interleave set to 0
3>    Bank 0 1024MB : 00000030.00000000 -> 00000030.3fffffff.
3>    Bank 2 1024MB : 00000032.00000000 -> 00000032.3fffffff.
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0>Memory interleave set to 0
0>    Bank 0 1024MB : 00000000.00000000 -> 00000000.3fffffff.
0>    Bank 2 1024MB : 00000002.00000000 -> 00000002.3fffffff.
0>INFO:
0>    POST Passed all devices.
0>
0>POST: Return to OBP.

SC Alert: Host System has Reset

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7480
PC = 0000.07ff.f000.62c8
PC = 0000.0000.0000.63c8
Find dropin, Copying Done, Size 0000.0000.0001.1d10
Diagnostic console initialized
Configuring system memory & CPU(s)

RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c80 TnPC=0000.0000.f000.4c84 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7480
PC = 0000.07ff.f000.62c8
PC = 0000.0000.0000.63c8
Find dropin, Copying Done, Size 0000.0000.0001.1d10
Diagnostic console initialized
Configuring system memory & CPU(s)

RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c80 TnPC=0000.0000.f000.4c84 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7480
PC = 0000.07ff.f000.62c8
PC = 0000.0000.0000.63c8
Find dropin, Copying Done, Size 0000.0000.0001.1d10
Diagnostic console initialized
Configuring system memory & CPU(s)

RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c80 TnPC=0000.0000.f000.4c84 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7480
PC = 0000.07ff.f000.62c8
PC = 0000.0000.0000.63c8
Find dropin, Copying Done, Size 0000.0000.0001.1d10
Diagnostic console initialized
Configuring system memory & CPU(s)

RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c80 TnPC=0000.0000.f000.4c84 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7480
PC = 0000.07ff.f000.62c8
PC = 0000.0000.0000.63c8
Find dropin, Copying Done, Size 0000.0000.0001.1d10
Diagnostic console initialized
Configuring system memory & CPU(s)

RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.420c TnPC=0000.0000.f000.4210 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c80 TnPC=0000.0000.f000.4c84 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.30.4.a 2010/01/06 14:45 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
  %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00b.505a %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags

最佳答案

查看完整内容

1、cpu 或者内存，你可以单放一个CPU启动看看。2、PROM没插好3、电池没电了4、主板坏了。

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2楼 [报告]

发表于 2013-04-08 10:04 |只看该作者

1、cpu 或者内存，你可以单放一个CPU启动看看。

2、PROM没插好

3、电池没电了

4、主板坏了。

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3楼 [报告]

发表于 2013-04-08 11:53 |只看该作者

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!

实战分享：从技术角度谈机器学习入门| 【大话IT】RadonDB低门槛向MySQL集群下战书 | ChinaUnix打赏功能已上线！ | 新一代分布式关系型数据库RadonDB知多少？

论坛徽章:: 0

4楼 [报告]

发表于 2013-04-08 12:43 |只看该作者

正常状况是cpu板有问题，但是这样的报错本来就是一个bug可能主板也不一定

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双鱼座
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5楼 [报告]

发表于 2013-04-08 12:44 |只看该作者

POST Passed all devices.
这个机器是肿么了要作POST？你是怎么设置的POST？

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6楼 [报告]

发表于 2013-04-08 13:06 |只看该作者

直接用钥匙转到最大化自检然后开机自检

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7楼 [报告]

发表于 2013-04-08 13:10 |只看该作者

你的alom版本多少？刷下。你的意思是你在循环出这个还是能到OK 无法引导？

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8楼 [报告]

发表于 2013-04-08 13:18 |只看该作者

回复 6# 鑫杰

到不了ok 开机启动就这样

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9楼 [报告]

发表于 2013-04-08 13:19 |只看该作者

会不会是scc卡的问题

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10楼 [报告]

发表于 2013-04-08 13:34 |只看该作者

Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!

这个就是从scc读不了东西，但是应该能到OK 吧。你吧钥匙放到诊断，然后不要拧回来看下。

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