AMD SOC团队近期招聘

nospecial

我们AMD上海site SOC team近期有数名职位空缺招聘，请感兴趣的筒子们速与我联系( mail : amd_srdc@126.com )。

形式：
        社会招聘，要求1年以上工作经验
职位：
        SOC integration engineer : 主要涉及综合/STA/LEC/MVRC/CDC/GCA等，要求一定的脚本能力(perl,shell,tcl...)
        SOC DV engineer : 主要涉及SOC chip level的test patten define以及verification的具体execution。
Title:
        不限，可以是junior，senior，staff，也可以是更high level，depends on your own capability

具体JD：
SOC Integration Engineer -->
The candidate is preferred to be MSEE or BSEE with several years experience in digital ASIC/SOC design engineering.

The candidate should have deep understanding on ASIC/SOC design flow and must be proficient in quite a lot of following skill sets:

1. RTL(verilog) coding and style checking
2. Scripts based on makefile, perl, TCL or csh/tcsh
3. Clock-domain-cross checking
4. Logic synthesis
5. Static timing analysis
6. Logic equivalency checking
7. ECO(engineering change order)
8. Top level integration, pad-ring design
9. Clock distribution



SOC DV engineer -->
The candidate will be employed in dGPU SoC level verification.

Key Job Functions:
- Understand the architecture and functionality of the chip
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/use the automated regression infrastructure setup for full chip functional verification.
- Help debug and correct functional errors in the design blocks, using logic abstraction, simulation and debug tools, based on good understanding of the architectural

specification, RTL and/or device level design of the block.
- Be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements

to support the design environment

Preferred Experience:
- Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Needs to have better understanding of Verification methodology and concepts.
- Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
- Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Proficient programming knowledge on Verilog,C++
- Knowledge on UPF based verification is a plus
- Design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Strong problem solving skills