求教SUN V480无显示无CONSOL只有RSC

flutter

偶有一台老SUN V480，最近想升级内存，装个SOLARIS 10，让它发挥点余热。

A板16根安装顺利，不料B板死活装上去无法识别，后来竟然系统亮起了黄灯。

现在的问题是：1，系统开机后亮故障黄灯，CPU板上绿灯亮，显示器无任何输出。

2，用笔记本接到后面CONSOLE口，也无任何输出。

3，用笔记本接到后面RSC CONSOLE，可以正常登录系统。

现在，偶如何拿到开机显示信息阿，比如报错一类的，如何开机自检阿。。。。

求教各位老大，谢谢！

calcm

哎，苦逼的孩纸，如果没记错的话，你把钥匙拧到诊断模式，console就有输出了。
能进系统，你也可以用eeprom吧output input定义到RSC的

flutter

  我把钥匙拧到“诊断”模式了，貌似显示器还是没有输出阿。。。。

我说的进系统是正常登录RSC，在RSC里竟然说系统是POWER OFF，很多命令不让用。。。。

calcm

POST时显示器肯定没输出啊，接串口啊

DC_楚楚

回复 3# flutter


    描述太多，你把rsc的输出情况贴出来嘛~

   诊断档输出在串口~  进入系统才会输出到显示器 ~

flutter

哎，折腾几天了，今天继续折腾。

再关机，再开机，RSC有自检信息，再接到CONSOLE，终于有了POST ：

rsc>
rsc>
rsc> console
Welcome to RSC bootmon v2.0.0

Reset register: e0000000 EHRS ESRS LLRS





RSC2 POST  -  Version 10-18-2000 0.7

Dual Port Memory Test, PASSED.

TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.

TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.

TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.

Memory Data Lines Test
Memory Data Lines Test, PASSED.

Memory Address Lines Test
  Slide address bits to test open address lines
  Test for shorted address lines
Memory Address Lines Test, PASSED.

Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.



Return to Boot Monitor for Handshake

RSC2 POST  -  Version 10-18-2000 0.7   Status = 00007fff

Returned from Boot Monitor and Handshake



Instruction CACHE Test
  DISABLE the I-CACHE
  ENABLE the I-CACHE
  Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.

Memory Cells Test
  Counting UP:    Write data:  00000000
  Counting DOWN:  Read - Verify - Write data:  ffffffff
  Counting UP:    Read - Verify - Write data:  55aa33cc
  Counting DOWN:  Read - Verify - Write data:  aa33cc66
  Counting UP:    Read - Verify - Write data:  33cc6699
  Counting DOWN:  Read - Verify - Write data:  cc669955
  Counting UP:    Read - Verify - Write data:  669955aa
  Counting DOWN:  Read - Verify - Write data:  9955aa33
  Counting UP:    Read - Verify - Write data:  f0f0f0f0
Memory Cells Test, PASSED.

Data CACHE Test
  Verify D-CACHE Performance Increase
    D-CACHE Performance Increase I-CACHE Disabled
    D-CACHE Performance Increase I-CACHE Enabled
  Verify D-CACHE Memory
Data CACHE Test, PASSED.

Main Sectors FLASH CRC Test
Main Sectors FLASH CRC Test, PASSED.

Load the RSC, then run the VxDiags

RSC version 2.2.3 (stdb)



Full VxDiag Tests

PCF8591 THERMISTOR TEST
PCF8591 THERMISTOR TEST, PASSED

BASIC TOD TEST
  Read the TOD Clock:        FRI APR 18 08:33:34 2014
  Wait, 1 - 3 seconds
  Read the TOD Clock:        FRI APR 18 08:33:36 2014
BASIC TOD TEST, PASSED

ETHERNET CPU LOOPBACK TEST
  50 BYTE PACKET   - a 0 in field of 1's.
  50 BYTE PACKET   - a 1 in field of 0's.
  900 BYTE PACKET  - pseudo-random data.
ETHERNET CPU LOOPBACK TEST, PASSED

MODEM PRESENT TEST
  Verify Modem is present
MODEM PRESENT TEST, PASSED

MODEM INIT and REGISTER TEST
  Check for VALID PCMCIA Address
  MODEM Register Test
MODEM INIT and REGISTER TEST, PASSED

MODEM TUPLES TEST
  Read TUPLES Data
  Verify TUPLES Data
MODEM TUPLES TEST, PASSED

Full VxDiag Tests - PASSED



    Status summary  -  Status = 7FFF

       VxDiag    -          -  PASSED
       POST      -          -  PASSED
       LOOPBACK  -          -  PASSED

       BATTERY   -          -  PASSED
       I2C       -          -  PASSED
       EPROM     -          -  PASSED
       FRU PROM  -          -  PASSED

       ETHERNET  -          -  PASSED
       MODEM     -          -  PASSED
       MAIN CRC  -          -  PASSED
       BOOT CRC  -          -  PASSED

       TTYD      -          -  PASSED
       TTYC      -          -  PASSED
       MEMORY    -          -  PASSED
       MPC860    -          -  PASSED


Please login: rscroot
Please Enter password:

rsc>
rsc>
rsc> show
page_enabled: false
page_verbose: false
mail_enabled: false
ip_mode: config
ppp_enabled: false
tpe_link_test: true
serial_baud: 9600
serial_parity: none
serial_stop: 1
serial_data: 8
modem_parity: none
modem_stop: 1
modem_data: 8
customerinfo: sun480
ip_addr: 202.114.89.100
ip_netmask: 255.255.255.128
ip_gateway: 202.114.89.1
mailhost:
mailuser:
page_info1:
page_init1:
page_password1:
page_parity1: even
page_stop1: 1
page_data1: 7
page_baud1: 9600
page_info2:
page_init2:
page_password2:
page_parity2: even
page_stop2: 1
page_data2: 7
page_baud2: 9600
ppp_local_ip_addr: 0.0.0.0
ppp_remote_ip_addr: 0.0.0.0
hostname: stdb
escape_char: ~
country_code: 001
rsc> poweron
Are you sure you want to turn your system power on (Yes/No)?  yes
rsc> 0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 3: 00000003.00000000 to 00000003.40
000000.
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is 7423.
0:0>The Memory's Content Size value is a0784.
0:0>Success...  Checksum on Memory Validated.
2:0>Safari quick check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
2:0>Safari full  check
2:0>     to IO-bridge_0
2:0>     to IO-bridge_1
2:0>Probe and Setup Memory
2:0>INFO:         1024MB Bank 0
2:0>INFO:         1024MB Bank 1
2:0>INFO:         1024MB Bank 2
2:0>INFO:         1024MB Bank 3
2:0>
2:0>Set Mailbox
0:0>Data Bitwalk on Slave 2
0:0>    Test Bank 0.
0:0>    Test Bank 1.
0:0>    Test Bank 2.
0:0>    Test Bank 3.
0:0>Address Bitwalk on Slave 2
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 0: 00000020.00000000 to 00000020.40
000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 1: 00000021.00000000 to 00000021.40
000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 2: 00000022.00000000 to 00000022.40
000000.
0:0>
0:0>INFO: Addr walk mem test on CPU 2:0 Bank 3: 00000023.00000000 to 00000023.40
000000.
2:0>Setup Final DMMU Entries
2:0>Map Slave POST to master memory
2:0>Print Mem Config
2:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2:0>Memory in non-interleave config:
2:0>    Bank 0   1024MB : 00000020.00000000 -> 00000020.40000000.
2:0>    Bank 1   1024MB : 00000021.00000000 -> 00000021.40000000.
2:0>    Bank 2   1024MB : 00000022.00000000 -> 00000022.40000000.
2:0>    Bank 3   1024MB : 00000023.00000000 -> 00000023.40000000.
0:0>Memory Block.....
2:0>Scrub Memory
0:0>Print Mem Config
0:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0:0>Memory in non-interleave config:
0:0>    Bank 0   1024MB : 00000000.00000000 -> 00000000.40000000.
0:0>    Bank 1   1024MB : 00000001.00000000 -> 00000001.40000000.
0:0>    Bank 2   1024MB : 00000002.00000000 -> 00000002.40000000.
0:0>    Bank 3   1024MB : 00000003.00000000 -> 00000003.40000000.
0:0>Scrub Memory
2:0>Quick Block Mem Test
2:0>Quick Test 16777216 bytes at 00000020.00000000
0:0>Quick Block Mem Test
0:0>Quick Test 16777216 bytes at 00000000.00600000
0:0>40% Done...
2:0>Flush Caches
0:0>Flush Caches
2:0>Get code in ecache.
0:0>Get code in ecache.
0:0>IO-Bridge Tests.....
0:0>IO-Bridge unit 0 init      test
0:0>IO-Bridge unit 1 init      test
0:0>IO-Bridge unit 0 reg       test
0:0>IO-Bridge unit 0 mem       test
0:0>IO-Bridge unit 0 PCI DMA A test
0:0>IO-Bridge unit 0 PCI DMA B test
0:0>IO-Bridge unit 0 PCI merg  test
0:0>IO-Bridge unit 0 PCI iommu test
0:0>IO-Bridge unit 0 PCI stc   test
0:0>IO-Bridge unit 0 interrupt test
0:0>IO-Bridge unit 1 reg       test
0:0>IO-Bridge unit 1 mem       test
0:0>IO-Bridge unit 1 PCI DMA C test
0:0>IO-Bridge unit 1 PCI DMA D test
0:0>IO-Bridge unit 1 PCI merg  test
0:0>IO-Bridge unit 1 PCI iommu test
0:0>IO-Bridge unit 1 PCI stc   test
0:0>IO-Bridge unit 1 interrupt test
2:0>IO-Bridge unit 0 init      test
2:0>IO-Bridge unit 0 PCI merg  test
2:0>IO-Bridge unit 0 interrupt test
2:0>IO-Bridge unit 1 init      test
2:0>IO-Bridge unit 1 PCI merg  test
2:0>IO-Bridge unit 1 interrupt test
2:0>FPU Registers and Data Path
0:0>FPU Registers and Data Path
2:0>FPU Move Registers
0:0>FPU Move Registers
2:0>FSR Read/Write
0:0>FSR Read/Write
2:0>FPU BLOCK REG TEST
0:0>FPU BLOCK REG TEST
0:0>
0:0>Motherboard/Centerplane Board Part Number:
0:0>    5016780-01-52
0:0>IO/Riser Board Part Number:
0:0>    5015820-04-55
0:0>CPUA Board Part Number:
0:0>    5016707-01-52
0:0>CPUB Board Part Number:
0:0>
0:0>INFO: Unpopulated Slot
0:0>Enable Errors.....
0:0>Turn IO-Bridge 0 errors on
0:0>Turn IO-Bridge 1 errors on
0:0>Turn CPU 0 errors on
0:0>Turn CPU 2 errors on
0:0>Turn Module A DCDS errors on
0:0>Turn DCS errors on
0:0>Turn DAR errors on
0:0>Turn error traps on
0:0>INFO:
0:0>    POST Passed all devices.
0:0>POST:       Return to OBP.


CPU0: System Power On Selftest Completed
    Pass/Fail Status  = 0000.0000.0000.0000
    ESB Overall Status  = ffff.ffff.ffff.ffff


<*>
POST Reset

@(#)OBP 4.13.2 2004/03/29 10:08 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Configuring CPUs..........
... CPU0 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU2 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00 Done
<*>
CPU Configuration Reset

@(#)OBP 4.13.2 2004/03/29 10:08 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Enabling Safari .......... CPU0 CPU2 Done
Probing Memory............
Probing CPU0 memory configuration
  NGDIMM#0 part# 501-5030-03 serial# S00959,  256MB + 256MB,  SC#0
  NGDIMM#1 part# 501-5030-03 serial# S0096J,  256MB + 256MB,  SC#0
  NGDIMM#2 part# 501-5030-03 serial# S0095H,  256MB + 256MB,  SC#0
  NGDIMM#3 part# 501-5030-03 serial# S0095N,  256MB + 256MB,  SC#0
  NGDIMM#4 part# 501-5030-03 serial# S00KNW,  256MB + 256MB,  SC#0
  NGDIMM#5 part# 501-5030-03 serial# S0086Y,  256MB + 256MB,  SC#0
  NGDIMM#6 part# 501-5030-03 serial# S00KM3,  256MB + 256MB,  SC#0
  NGDIMM#7 part# 501-5030-03 serial# S00891,  256MB + 256MB,  SC#0
Probing CPU2 memory configuration
  NGDIMM#0 part# 501-5030-03 serial# S0095D,  256MB + 256MB,  SC#0
  NGDIMM#1 part# 501-5030-03 serial# S0097D,  256MB + 256MB,  SC#0
  NGDIMM#2 part# 501-5030-03 serial# S0095B,  256MB + 256MB,  SC#0
  NGDIMM#3 part# 501-5030-03 serial# S0095G,  256MB + 256MB,  SC#0
  NGDIMM#4 part# 501-5030-03 serial# S00956,  256MB + 256MB,  SC#0
  NGDIMM#5 part# 501-5030-03 serial# S0095J,  256MB + 256MB,  SC#0
  NGDIMM#6 part# 501-5030-03 serial# S00951,  256MB + 256MB,  SC#0
  NGDIMM#7 part# 501-5030-03 serial# S0094Y,  256MB + 256MB,  SC#0
Mungeing Memory...........Done
HiMem: 0000.00a0.0000.0000, size: 0000.0002.0000.0000
Configuring Memory........ CPU0 CPU2 Done
Init ICache/etc........... CPU0 CPU2 Done
Init ECache Tags.......... CPU0 CPU2 Done
Clearing TLBs............. CPU0 CPU2 Done
Setup I/DTLBs............. CPU0 CPU2 Done
Enabling Cache/MMUs....... CPU0 CPU2 Done
Init ECache Data.......... CPU0 CPU2 Done
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 96KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.5ea8.58ab;  ROM CRC = 0000.0000.5ea8.58ab
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.0300 (449KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0
Boot  CPU2 starting Forth at 0000.0000.f000.00e0

ttya initialized
Probing gptwo at 0,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 1,0 Nothing there
Probing gptwo at 2,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 3,0 Nothing there
Probing gptwo at 4,0 Nothing there
Probing gptwo at 5,0 Nothing there
Probing gptwo at 6,0 Nothing there
Probing gptwo at 7,0 Nothing there
Probing gptwo at 8,0 pci pci
Probing gptwo at 9,0 pci pci
Loading Support Packages: obp-tftp kbd-translator SUNW,i2c-ram-device
   SUNW,fru-device
Loading onboard drivers: ebus flashprom bbc power i2c fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru fru nvram idprom
   fru fru i2c temperature temperature temperature ioexp ioexp ioexp
   temperature ioexp ioexp ioexp ioexp temperature-sensor fru fru fru
   fru fru rscrtc rtc gpio pmc rsc-control rsc-console serial
Memory Configuration:
CPU0 Bank0  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #0
CPU0 Bank1  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #2
CPU0 Bank2  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #4
CPU0 Bank3  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #6
CPU2 Bank0  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #1
CPU2 Bank1  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #3
CPU2 Bank2  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #5
CPU2 Bank3  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #7
Probing /pci@8,600000 Device 1  Nothing there
Probing /pci@8,600000 Device 2  Nothing there
Probing /pci@8,700000 Device 2  SUNW,XVR-100
Probing /pci@8,700000 Device 3  SUNW,qlc fp disk
Probing /pci@8,700000 Device 4  SUNW,qlc fp disk
Probing /pci@8,700000 Device 5  pci
Probing /pci@8,700000/pci@5 Device 0  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 1  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 2  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 3  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 4  Nothing there
Probing /pci@8,700000/pci@5 Device 5  Nothing there
Probing /pci@8,700000/pci@5 Device 6  Nothing there
Probing /pci@8,700000/pci@5 Device 7  Nothing there
Probing /pci@8,700000/pci@5 Device 8  Nothing there
Probing /pci@8,700000/pci@5 Device 9  Nothing there
Probing /pci@8,700000/pci@5 Device a  Nothing there
Probing /pci@8,700000/pci@5 Device b  Nothing there
Probing /pci@8,700000/pci@5 Device c  Nothing there
Probing /pci@8,700000/pci@5 Device d  Nothing there
Probing /pci@8,700000/pci@5 Device e  Nothing there
Probing /pci@8,700000/pci@5 Device f  Nothing there
Probing /pci@8,700000 Device 6  ide disk cdrom
Probing /pci@9,600000 Device 1  network
Probing /pci@9,600000 Device 2  SUNW,qlc fp disk
Probing /pci@9,700000 Device 1  usb keyboard mouse
Probing /pci@9,700000 Device 2  network


<*>
Firmware I/O Diagnostics Reset

@(#)OBP 4.13.2 2004/03/29 10:08 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU0 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU2 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Enabling Safari .......... CPU0 CPU2 Done
Init ICache/etc........... CPU0 CPU2 Done
Init ECache Tags.......... CPU0 CPU2 Done
Clearing TLBs............. CPU0 CPU2 Done
Setup I/DTLBs............. CPU0 CPU2 Done
Enabling Cache/MMUs....... CPU0 CPU2 Done
Init ECache Data.......... CPU0 CPU2 Done
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 96KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.5ea8.58ab;  ROM CRC = 0000.0000.5ea8.58ab
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.0300 (449KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0
Boot  CPU2 starting Forth at 0000.0000.f000.00e0

ttya initialized
Probing gptwo at 0,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 1,0 Nothing there
Probing gptwo at 2,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 3,0 Nothing there
Probing gptwo at 4,0 Nothing there
Probing gptwo at 5,0 Nothing there
Probing gptwo at 6,0 Nothing there
Probing gptwo at 7,0 Nothing there
Probing gptwo at 8,0 pci pci
Probing gptwo at 9,0 pci pci
Loading Support Packages: obp-tftp kbd-translator SUNW,i2c-ram-device
   SUNW,fru-device
Loading onboard drivers: ebus flashprom bbc power i2c fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru fru nvram idprom
   fru fru i2c temperature temperature temperature ioexp ioexp ioexp
   temperature ioexp ioexp ioexp ioexp temperature-sensor fru fru fru
   fru fru rscrtc rtc gpio pmc rsc-control rsc-console serial
Memory Configuration:
CPU0 Bank0  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #0
CPU0 Bank1  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #2
CPU0 Bank2  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #4
CPU0 Bank3  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #6
CPU2 Bank0  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #1
CPU2 Bank1  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #3
CPU2 Bank2  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #5
CPU2 Bank3  256 +  256 +  256 +  256 :    1GB @  a000000000  8-way #7
Probing /pci@8,600000 Device 1  Nothing there
Probing /pci@8,600000 Device 2  Nothing there
Probing /pci@8,700000 Device 2  SUNW,XVR-100
Probing /pci@8,700000 Device 3  SUNW,qlc fp disk
Probing /pci@8,700000 Device 4  SUNW,qlc fp disk
Probing /pci@8,700000 Device 5  pci
Probing /pci@8,700000/pci@5 Device 0  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 1  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 2  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 3  pci108e,1000 SUNW,qfe
Probing /pci@8,700000/pci@5 Device 4  Nothing there
Probing /pci@8,700000/pci@5 Device 5  Nothing there
Probing /pci@8,700000/pci@5 Device 6  Nothing there
Probing /pci@8,700000/pci@5 Device 7  Nothing there
Probing /pci@8,700000/pci@5 Device 8  Nothing there
Probing /pci@8,700000/pci@5 Device 9  Nothing there
Probing /pci@8,700000/pci@5 Device a  Nothing there
Probing /pci@8,700000/pci@5 Device b  Nothing there
Probing /pci@8,700000/pci@5 Device c  Nothing there
Probing /pci@8,700000/pci@5 Device d  Nothing there
Probing /pci@8,700000/pci@5 Device e  Nothing there
Probing /pci@8,700000/pci@5 Device f  Nothing there
Probing /pci@8,700000 Device 6  ide disk cdrom
Probing /pci@9,600000 Device 1  network
Probing /pci@9,600000 Device 2  SUNW,qlc fp disk
Probing /pci@9,700000 Device 1  usb keyboard mouse
Probing /pci@9,700000 Device 2  network

flutter

0:0>Motherboard/Centerplane Board Part Number:
0:0>    5016780-01-52
0:0>IO/Riser Board Part Number:
0:0>    5015820-04-55
0:0>CPUA Board Part Number:
0:0>    5016707-01-52
0:0>CPUB Board Part Number:
0:0>
0:0>INFO: Unpopulated Slot
0:0>Enable Errors.....

貌似CPUB都没有识别到阿。。。啥情况？拆下来装上去就不认识了??

119beyond

你重新核查一下，看有没有插倒，或者是没有插好

flutter

把A和B板换了个位置，重新开机自检，信息如下：


<*>
Hardware Power On

@(#)OBP 4.13.2 2004/03/29 10:08 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online: CPU1 CPU3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done

Probing Centerplane....part# 501-6780-01 serial# 004092
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 058256
Probing System RSC.....part# 501-5856-06 serial# 237300
Probing PwrDistBoard...part# 375-3006-05 serial# M48733
Probing PowerSupply0...part# 300-1480-05 serial# N30911
Probing PowerSupply1...part# 300-1480-05 serial# N32209
Probing FCAL BPlane0...part# 501-5822-04 serial# 058772
Probing GPTwo Slot A...part# 501-6707-01 serial# 001927
WARNING: Module Power-Fault
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  CPU rated speed 1050MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...part# 501-6707-01 serial# 001758
  Safari min 100MHz, cumulative 100MHz;  max 150MHz, cumulative 150MHz
  CPU rated speed 1050MHz; ECache 8MB 3.3ns

Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU1 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU3 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00 Done
Setting system speed (and resetting)...
<*>
Set Speed Reset

@(#)OBP 4.13.2 2004/03/29 10:08 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online:  CPU1 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.1) 7:1 1050MHz 8MB 4:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.2042
1:0>
1:0>@(#) Sun Fire[TM] V480 POST 4.13.0 2004/02/12 19:17
       /export/common-source/firmware_re/post/post-build-4.13.0/Camelot/cstone/integrated  (firmware_re)  
1:0>Copyright &copy; 2004 Sun Microsystems, Inc. All rights reserved
  SUN PROPRIETARY/CONFIDENTIAL.
  Use is subject to license terms.
1:0>Jump from OBP->POST.
1:0>Keyswitch in DIAGNOSTIC POSITION.
1:0>Diag level set to MIN.
1:0>Verbosity level set to 0.
1:0>MFG scrpt mode set NORM
1:0>I/O port set to serial TTYA.
1:0>
1:0>Start selftest...
1:0>CPUs present in system: 1:0 3:0
1:0>Test CPU(s).....
1:0>Init CPU
1:0>    UltraSparc_III_plus Version 11.1
1:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0>    Size = 00000000.00800000...
1:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
3:0>Init CPU
3:0>    UltraSparc_III_plus Version 11.1
3:0>DMMU Registers Access
3:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB TAGS Access
3:0>IMMU Registers Access
3:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB TAGS Access
3:0>Probe Ecache
3:0>    Size = 00000000.00800000...
3:0>Ecache Data Bitwalk
3:0>Ecache Address Bitwalk
3:0>Scrub and Setup Ecache
3:0>Setup and Enable DMMU
3:0>Setup DMMU Miss Handler
3:0>Test and Init Temp Mailbox
1:0>Init Scan/I2C.....
1:0>Initializing Scan Database
1:0>Mask DAR errors off
1:0>Init CDX DTL
1:0>Init DAR DTL
1:0>Enable Partial DAR error
1:0>Init DCS DTL
1:0>Init I2C
1:0>Unquiesce Safari
1:0>Margin all voltages to nominal
1:0>Scan ring integrity
1:0>
1:0>INFO: H/W under test = CPU Board Slot A (Cheetah 0, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
1:0>
1:0>INFO: H/W under test = CPU Board Slot A (Cheetah 2, SRAMs) Scan Ring NOT Present or Shut OFF
1:0>Set Trip Temp CPU 1 to 110C
1:0>Set Trip Temp CPU 3 to 110C
1:0>FRI APR  18 4:13:39 GMT 14
1:0>Safari quick check
1:0>     to IO-bridge_0
1:0>     to IO-bridge_1
1:0>Safari full  check
1:0>     to IO-bridge_0
1:0>     to IO-bridge_1
1:0>Disable CPU 1 error checking
1:0>Disable CPU 3 error checking
1:0>Basic Memory Test.....
1:0>Probe and Setup Memory
1:0>INFO:         1024MB Bank 0
1:0>INFO:         1024MB Bank 1
1:0>INFO:         1024MB Bank 2
1:0>INFO:         1024MB Bank 3
1:0>
1:0>Data Bitwalk on Master
1:0>    Test Bank 0.
1:0>    Test Bank 1.
1:0>    Test Bank 2.
1:0>    Test Bank 3.
1:0>Address Bitwalk on Master
1:0>
1:0>INFO: Addr walk mem test on CPU 1:0 Bank 0: 00000010.00000000 to 00000010.40000000.
1:0>
1:0>INFO: Addr walk mem test on CPU 1:0 Bank 1: 00000011.00000000 to 00000011.40000000.
1:0>
1:0>INFO: Addr walk mem test on CPU 1:0 Bank 2: 00000012.00000000 to 00000012.40000000.
1:0>
1:0>INFO: Addr walk mem test on CPU 1:0 Bank 3: 00000013.00000000 to 00000013.40000000.
1:0>Set Mailbox
1:0>Setup Final DMMU Entries
1:0>Post Image Region Scrub
1:0>Run POST from Memory
1:0>Verifying checksum on copied image.
1:0>The Memory's CHECKSUM value is 7423.
1:0>The Memory's Content Size value is a0784.
1:0>Success...  Checksum on Memory Validated.
3:0>Safari quick check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
3:0>Safari full  check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
3:0>Probe and Setup Memory
3:0>INFO:         1024MB Bank 0
3:0>INFO:         1024MB Bank 1
3:0>INFO:         1024MB Bank 2
3:0>INFO:         1024MB Bank 3
3:0>
3:0>Set Mailbox
1:0>Data Bitwalk on Slave 3
1:0>    Test Bank 0.
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000030.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000030.001b0040=ffffffff.fffffffe.
1:0>            Address 00000030.001b0048=ffffffff.ffffffff.
1:0>            Address 00000030.001b0050=ffffffff.ffffffff.
1:0>            Address 00000030.001b0058=ffffffff.ffffffff.
1:0>            Address 00000030.001b0060=ffffffff.ffffffff.
1:0>            Address 00000030.001b0068=ffffffff.ffffffff.
1:0>            Address 00000030.001b0070=ffffffff.ffffffff.
1:0>            Address 00000030.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 0 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000030.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000030.001b0040=ffffffff.fffffffd.
1:0>            Address 00000030.001b0048=ffffffff.ffffffff.
1:0>            Address 00000030.001b0050=ffffffff.ffffffff.
1:0>            Address 00000030.001b0058=ffffffff.ffffffff.
1:0>            Address 00000030.001b0060=ffffffff.ffffffff.
1:0>            Address 00000030.001b0068=ffffffff.ffffffff.
1:0>            Address 00000030.001b0070=ffffffff.ffffffff.
1:0>            Address 00000030.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 0 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>    Test Bank 1.
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 0 Dimm 3, J8000 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000031.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000031.001b0040=ffffffff.fffffffe.
1:0>            Address 00000031.001b0048=ffffffff.ffffffff.
1:0>            Address 00000031.001b0050=ffffffff.ffffffff.
1:0>            Address 00000031.001b0058=ffffffff.ffffffff.
1:0>            Address 00000031.001b0060=ffffffff.ffffffff.
1:0>            Address 00000031.001b0068=ffffffff.ffffffff.
1:0>            Address 00000031.001b0070=ffffffff.ffffffff.
1:0>            Address 00000031.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 1 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000031.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000031.001b0040=ffffffff.fffffffd.
1:0>            Address 00000031.001b0048=ffffffff.ffffffff.
1:0>            Address 00000031.001b0050=ffffffff.ffffffff.
1:0>            Address 00000031.001b0058=ffffffff.ffffffff.
1:0>            Address 00000031.001b0060=ffffffff.ffffffff.
1:0>            Address 00000031.001b0068=ffffffff.ffffffff.
1:0>            Address 00000031.001b0070=ffffffff.ffffffff.
1:0>            Address 00000031.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 1 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>    Test Bank 2.
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 1 Dimm 3, J8200 side 1
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000032.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000032.001b0040=ffffffff.fffffffe.
1:0>            Address 00000032.001b0048=ffffffff.ffffffff.
1:0>            Address 00000032.001b0050=ffffffff.ffffffff.
1:0>            Address 00000032.001b0058=ffffffff.ffffffff.
1:0>            Address 00000032.001b0060=ffffffff.ffffffff.
1:0>            Address 00000032.001b0068=ffffffff.ffffffff.
1:0>            Address 00000032.001b0070=ffffffff.ffffffff.
1:0>            Address 00000032.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 2 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000032.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000032.001b0040=ffffffff.fffffffd.
1:0>            Address 00000032.001b0048=ffffffff.ffffffff.
1:0>            Address 00000032.001b0050=ffffffff.ffffffff.
1:0>            Address 00000032.001b0058=ffffffff.ffffffff.
1:0>            Address 00000032.001b0060=ffffffff.ffffffff.
1:0>            Address 00000032.001b0068=ffffffff.ffffffff.
1:0>            Address 00000032.001b0070=ffffffff.ffffffff.
1:0>            Address 00000032.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 2 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>    Test Bank 3.
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 2 Dimm 3, J8000 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000033.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000033.001b0040=ffffffff.fffffffe.
1:0>            Address 00000033.001b0048=ffffffff.ffffffff.
1:0>            Address 00000033.001b0050=ffffffff.ffffffff.
1:0>            Address 00000033.001b0058=ffffffff.ffffffff.
1:0>            Address 00000033.001b0060=ffffffff.ffffffff.
1:0>            Address 00000033.001b0068=ffffffff.ffffffff.
1:0>            Address 00000033.001b0070=ffffffff.ffffffff.
1:0>            Address 00000033.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 3 Dimm 3, J8200 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 3 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 3 Dimm 3, J8200 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 3 Dimm 3, J8200 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000032
        Trap PC        ffffffff.f01214cc
        Trap Level     00000000.00000001
        AFSR           00100002.00000040
        AFAR           00000033.001b0040
1:0>END_WARNING

1:0>    PRIV bit: Privileged code access error(s)
1:0>    CE bit: Correctable system data ECC error
1:0>
        Failed cache line data:
1:0>            Address 00000033.001b0040=ffffffff.fffffffd.
1:0>            Address 00000033.001b0048=ffffffff.ffffffff.
1:0>            Address 00000033.001b0050=ffffffff.ffffffff.
1:0>            Address 00000033.001b0058=ffffffff.ffffffff.
1:0>            Address 00000033.001b0060=ffffffff.ffffffff.
1:0>            Address 00000033.001b0068=ffffffff.ffffffff.
1:0>            Address 00000033.001b0070=ffffffff.ffffffff.
1:0>            Address 00000033.001b0078=ffffffff.ffffffff.
1:0>    AFSR check after re-reading data:
1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 3 Dimm 3, J8200 side 2
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = DIMM failure Bank 3 DIMM 3 Pin 45
1:0>END_ERROR

1:0>
1:0>WARNING: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3 Bank 3 Dimm 3, J8200 side 2
1:0>MSG = Data or Instruction Access Error,
        Trap Type      00000000.00000063
        Trap PC        ffffffff.f01214e0
        Trap Level     00000000.00000001
        AFSR           00000000.00000000
        AFAR           00000000.00000000
1:0>END_WARNING

1:0>    No Errors in afsr reg
1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG =
         *** Test Failed!! ***

1:0>END_ERROR

1:0>
1:0>ERROR: TEST = Data Bitwalk on Slave 3
1:0>H/W under test = CPU3, All CPU3 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = ERROR:        Memory error on master CPU, rolling over to new master.
1:0>END_ERROR
             &yacute;3:0>Soft Reset.
3:0>
3:0>Start selftest...
3:0>CPUs present in system: 1:0 3:0
3:0>Test CPU(s).....
3:0>Init CPU
3:0>    UltraSparc_III_plus Version 11.1
3:0>DMMU Registers Access
3:0>DMMU TLB DATA RAM Access
3:0>DMMU TLB TAGS Access
3:0>IMMU Registers Access
3:0>IMMU TLB DATA RAM Access
3:0>IMMU TLB TAGS Access
3:0>Probe Ecache
3:0>    Size = 00000000.00800000...
3:0>Ecache Data Bitwalk
3:0>Ecache Address Bitwalk
3:0>Scrub and Setup Ecache
3:0>Setup and Enable DMMU
3:0>Setup DMMU Miss Handler
3:0>Test and Init Temp Mailbox
1:0>Init CPU
1:0>    UltraSparc_III_plus Version 11.1
1:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0>    Size = 00000000.00800000...
1:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
3:0>Init Scan/I2C.....
3:0>Initializing Scan Database
3:0>Mask DAR errors off
3:0>Init CDX DTL
3:0>Init DAR DTL
3:0>Enable Partial DAR error
3:0>Init DCS DTL
3:0>Init I2C
3:0>Unquiesce Safari
3:0>Margin all voltages to nominal
3:0>Scan ring integrity
3:0>
3:0>INFO: H/W under test = CPU Board Slot A (Cheetah 0, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
3:0>
3:0>INFO: H/W under test = CPU Board Slot A (Cheetah 2, SRAMs) Scan Ring NOT Present or Shut OFF
3:0>Set Trip Temp CPU 1 to 110C
3:0>Set Trip Temp CPU 3 to 110C
3:0>FRI APR  18 4:15:02 GMT 14
3:0>Safari quick check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
3:0>Safari full  check
3:0>     to IO-bridge_0
3:0>     to IO-bridge_1
3:0>Disable CPU 1 error checking
3:0>Disable CPU 3 error checking
3:0>Basic Memory Test.....
3:0>Probe and Setup Memory
3:0>
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = No Memory Detected
3:0>END_ERROR

3:0>
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG =
         *** Test Failed!! ***

3:0>END_ERROR

3:0>
3:0>ERROR: TEST = Probe and Setup Memory
3:0>H/W under test = CPU3, All CPU3 Memory
3:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
3:0>MSG = ERROR:        Memory error on master CPU, rolling over to new master.
3:0>END_ERROR

3:0>ERROR:      No good CPUs left!  Calling debug menu.
3:0>    0       Peek/Poke interface
3:0>    1       Dump DAR Error Bits
3:0>    2       Dump Scan Chain
3:0>    3       Dump CPU Regs
3:0>    4       Dump BBC Regs
3:0>    5       Dump Mem Controller Regs
3:0>    6       Dump Valid DMMU entries
3:0>    7       Dump IMMU entries
3:0>    8       Dump Struct Info
3:0>    9       Dump Mailbox
3:0>    a       Dump IO-Bridge regs unit 0
3:0>    b       Dump IO-Bridge regs unit 1
3:0>    c       Allow other CPUs to print
3:0>    d       Do soft reset
3:0>    ?       Help
3:0>
3:0>Selection:

flutter

Probing GPTwo Slot A...part# 501-6707-01 serial# 001927
WARNING: Module Power-Fault

调换后，B板认识了，但说是电源模块失效？？B板的CPU/MEM还是没有识别

求解答。