ARM linux下的页表问题，百思不得其解。

求linux注释

ARM处理器的一级页表有4096个描述符。开启MMU后，虚拟地址的高12位作为索引值（虚拟地址>>20）加上存放在CP15的C2里的页表地址可得到一级页表项的地址。

而linux里arm处理器的获取页表项却是这么定义的，如下：

1. #define PMD_SHIFT        21
   
2. #define PGDIR_SHIFT        21
   
3. 
   
4. #define pgd_index(addr)        ((addr) >> PGDIR_SHIFT)  /* 虚拟地址 >> 21 取出虚拟地址对应的页表项？ */
   
5. #define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr)) /* addr是传入的欲取得页表项的虚拟地址；mm->pgd是页表基地址 */

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linux里为什么要把虚拟地址右移21位？不应该是右移20位吗？

Tinnal

回复 1# 求linux注释

1. /*
   
2. * Hardware-wise, we have a two level page table structure, where the first
   
3. * level has 4096 entries, and the second level has 256 entries.  Each entry
   
4. * is one 32-bit word.  Most of the bits in the second level entry are used
   
5. * by hardware, and there aren't any "accessed" and "dirty" bits.
   
6. *
   
7. * Linux on the other hand has a three level page table structure, which can
   
8. * be wrapped to fit a two level page table structure easily - using the PGD
   
9. * and PTE only.  However, Linux also expects one "PTE" table per page, and
   
10. * at least a "dirty" bit.
    
11. *
    
12. * Therefore, we tweak the implementation slightly - we tell Linux that we
    
13. * have 2048 entries in the first level, each of which is 8 bytes (iow, two
    
14. * hardware pointers to the second level.)  The second level contains two
    
15. * hardware PTE tables arranged contiguously, followed by Linux versions
    
16. * which contain the state information Linux needs.  We, therefore, end up
    
17. * with 512 entries in the "PTE" level.
    
18. *
    
19. * This leads to the page tables having the following layout:
    
20. *
    
21. *    pgd             pte
    
22. * |        |
    
23. * +--------+ +0
    
24. * |        |-----> +------------+ +0
    
25. * +- - - - + +4    |  h/w pt 0  |
    
26. * |        |-----> +------------+ +1024
    
27. * +--------+ +8    |  h/w pt 1  |
    
28. * |        |       +------------+ +2048
    
29. * +- - - - +       | Linux pt 0 |
    
30. * |        |       +------------+ +3072
    
31. * +--------+       | Linux pt 1 |
    
32. * |        |       +------------+ +4096
    
33. *
    
34. * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
    
35. * PTE_xxx for definitions of bits appearing in the "h/w pt".
    
36. *
    
37. * PMD_xxx definitions refer to bits in the first level page table.
    
38. *
    
39. * The "dirty" bit is emulated by only granting hardware write permission
    
40. * iff the page is marked "writable" and "dirty" in the Linux PTE.  This
    
41. * means that a write to a clean page will cause a permission fault, and
    
42. * the Linux MM layer will mark the page dirty via handle_pte_fault().
    
43. * For the hardware to notice the permission change, the TLB entry must
    
44. * be flushed, and ptep_set_access_flags() does that for us.
    
45. *
    
46. * The "accessed" or "young" bit is emulated by a similar method; we only
    
47. * allow accesses to the page if the "young" bit is set.  Accesses to the
    
48. * page will cause a fault, and handle_pte_fault() will set the young bit
    
49. * for us as long as the page is marked present in the corresponding Linux
    
50. * PTE entry.  Again, ptep_set_access_flags() will ensure that the TLB is
    
51. * up to date.
    
52. *
    
53. * However, when the "young" bit is cleared, we deny access to the page
    
54. * by clearing the hardware PTE.  Currently Linux does not flush the TLB
    
55. * for us in this case, which means the TLB will retain the transation
    
56. * until either the TLB entry is evicted under pressure, or a context
    
57. * switch which changes the user space mapping occurs.
    
58. */

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Tinnal

Linux自己做了一个假的软件页表，一级页表有2046项（因此右移了21位），每个二级页表有512项。对应真实的硬件页表，一级页表有1024项，每个二级页表有256项。

为什么这么折腾，代码里头就说得很清楚。主要原因有：
1. However, Linux also expects one "PTE" table per page,  -- Linux都假定每一级的页表占用一页内存，而硬件只需要1024字节，这样太浪费了。
2. and  at least a "dirty" bit.  --硬件的页表里没有Linux必须的dirty位（基实还缺accessed位），必须进行软件模拟。

因此就这么折腾罗。

详细的清况，就得你自己好好研究一下代码了。

lieye_leaves

我最近也在看这个问题，为什么linxu二级页表转化的时候 采用 11bit +9bit + 12bit，因为我查阅ARM书籍，介绍ARM上的MMU二级页表转化是采用
大页地址变化过程 12+4+16
小页地址变化过程 12+8+12
极小页变化过程    12+10+10
为什么linux的分页与硬件不一致？他转化的时候硬件MMU是否支持，它是如何工作的呢？

mysky0407

为什么是11bit +9bit + 12bit

1）11bit
ARM L1页表表项实际为4096 条* 4字节 == 16KB ，但LINUX实现定义成 2048 条 * 8字节 = 16KB，2048 = 2^11，所以是11不是12
2）9bit
由1可知：设计L1表项为2048，则L2每次映射空间由1MB变成2MB（2048 * 2MB = 4GB），即L2表项条数为2MB/4字节 = 512 = 2^9;
3）12bit
页大小为4KB = 2^12

lieye_leaves 发表于 2015-04-04 15:24
我最近也在看这个问题，为什么linxu二级页表转化的时候 采用 11bit +9bit + 12bit，因为我查阅ARM书籍，介绍 ...